參數(shù)資料
型號(hào): SRC4194IPAGT
英文描述: 4-Channel, Asynchronous Sample Rate Converter
中文描述: 4通道,異步采樣率轉(zhuǎn)換器
文件頁(yè)數(shù): 23/40頁(yè)
文件大?。?/td> 502K
代理商: SRC4194IPAGT
"#$%#
SBFS025A JUNE 2004 REVISED JULY 2004
www.ti.com
23
Left Channel
(a) LeftJustified Data Format
(b) RightJustified Data Format
Right Channel
LRCKI
BCKI
SDIN
MSB
LSB
LSB
MSB
LRCKI
BCKI
SDIN
MSB
MSB
LSB
LSB
(c) I
2
S Data Format
1/f
S
LRCKI
BCKI
SDIN
MSB
LSB
MSB
LSB
Figure 4. Input Data Formats
t
LRIS
t
SIH
t
LDIS
t
SIL
t
LDIH
LRCKI
BCKI
SDIN
Figure 5. Input Port Timing
Table 2 illustrates the data format selection for the input
port. For Hardware mode, the IFMTA0 (pin 1), IFMTA1
(pin 2), and IFMTA2 (pin 3) inputs are utilized to set the
input port data format for SRC A. IFMTB0 (pin 48), IFMTB1
(pin 47), and IFMTB2 (pin 46) are utilized to set the input
port data format for SRC B.
Table 2. Input Port Data Format Selection (x = A or B)
IFMTx2
0
0
0
0
1
1
1
1
IFMTx1
0
0
1
1
0
0
1
1
IFMTx0
0
1
0
1
0
1
0
1
INPUT PORT DATA FORMAT
24-Bit Left-Justified
24-Bit I2S
Unused
Unused
16-Bit Right-Justified
18-Bit Right-Justified
20-Bit Right-Justified
24-Bit Right-Justified
In Software mode, the IFMT[2:0] bits in Control Register 3
are used to select the data format for the SRC A and
SRC B register banks. The default format is 24-bit
Left-Justified.
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