2011 Silicon Storage Technology, Inc.
DS25088A
10/11
8
FlashFlex MCU
SST89E52RC / SST89E54RC
Data Sheet
A Microchip Technology Company
Memory Organization
The device has separate address spaces for program and data memory.
Program Flash Memory
There are two internal flash memory partitions in the device. The primary flash memory partition (Par-
tition 0) has 16/8 KByte. The secondary flash memory partition (Partition 1) has 1 KByte. The total
flash memory space of both partitions can be used as a contiguous code storage.
The 16K/8K x8 primary flash partition is organized as 128/64 sectors, each sector consists of 128
Bytes. The primary partition is divided into four logical pages as shown in Figure 5
The 1K x8 secondary flash partition is organized as 8 sectors, each sector consists also of 128 Bytes.
For both partitions, the 7 least significant program address bits select the byte within the sector. The
remainder of the program address bits select the sector within the partition.
Data RAM Memory
The data RAM has 512 Bytes of internal memory. The first 256 Bytes are available by default. The sec-
ond 256 Bytes are enabled by clearing the EXTRAM bit in the AUXR register. The RAM can be
addressed up to 64 KByte for external data memory.
Expanded Data RAM Addressing
The SST89E5xRC have the capability of 512 Bytes of RAM. See Figure 4.
The device has four sections of internal data memory:
1.
The lower 128 Bytes of RAM (00H to 7FH) are directly and indirectly addressable.
2.
The higher 128 Bytes of RAM (80H to FFH) are indirectly addressable.
3.
The special function registers (80H to FFH) are directly addressable only.
4.
The expanded RAM of 256 Bytes (00H to FFH) is indirectly addressable by the move
external instruction (MOVX) and clearing the EXTRAM bit. (See “Auxiliary Register
(AUXR)” in Section , “Special Function Registers”)
Since the upper 128 bytes occupy the same addresses as the SFRs, the RAM must be accessed indi-
rectly. The RAM and SFRs space are physically separate even though they have the same addresses.
When instructions access addresses in the upper 128 bytes (above 7FH), the MCU determines
whether to access the SFRs or RAM by the type of instruction given. If it is indirect, then RAM is
accessed. If it is direct, then an SFR is accessed. See the examples below.
Indirect Access:
MOV@R0, #data; R0 contains 90H
Register R0 points to 90H which is located in the upper address range. Data in “#data” is written to
RAM location 90H rather than port 1.
Direct Access:
MOV90H, #data; write data to P1
Data in “#data” is written to port 1. Instructions that write directly to the address write to the SFRs.