參數(shù)資料
型號(hào)： SST89V54RD-33-C-PIE
廠商： Microchip Technology
文件頁(yè)數(shù)： 3/92頁(yè)
文件大?。?/td> 0K
描述： IC MCU 8BIT 24KB FLASH 40PDIP
標(biāo)準(zhǔn)包裝： 9
系列： FlashFlex®
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 16KB（16K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大?。?/td> 8K x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
2011 Silicon Storage Technology, Inc.
DS25087A
10/11
11
FlashFlex MCU
SST89V54RD2/RD / SST89V58RD2/RD
Not Recommended for New Designs
A Microchip Technology Company
Reset Configuration of Program Memory Block Switching
Program memory block switching is initialized after reset according to the state of the Start-up Config-
uration bit SC0 and/or SC1. The SC0 and SC1 bits are programmed via an external host mode com-
mand or an IAP Mode command. See Table 13.
Once out of reset, the SFCF[0] bit can be changed dynamically by the program for desired effects.
Changing SFCF[0] will not change the SC0 bit.
Caution must be taken when dynamically changing the SFCF[0] bit. Since this will cause different
physical memory to be mapped to the logical program address space. The user must avoid executing
block switching instructions within the address range 0000H to 1FFFH.
Data RAM Memory
The data RAM has 1024 bytes of internal memory. The RAM can be addressed up to 64KB for external
data memory.
Expanded Data RAM Addressing
The SST89V5xRDx both have the capability of 1K of RAM. See Figure 7.
The device has four sections of internal data memory:
1.
The lower 128 Bytes of RAM (00H to 7FH) are directly and indirectly addressable.
2.
The higher 128 Bytes of RAM (80H to FFH) are indirectly addressable.
3.
The special function registers (80H to FFH) are directly addressable only.
4.
The expanded RAM of 768 Bytes (00H to 2FFH) is indirectly addressable by the move
external instruction (MOVX) and clearing the EXTRAM bit. (See “Auxiliary Register
(AUXR)” in Section , “Special Function Registers”)
Since the upper 128 bytes occupy the same addresses as the SFRs, the RAM must be accessed indi-
rectly. The RAM and SFRs space are physically separate even though they have the same addresses.
When instructions access addresses in the upper 128 bytes (above 7FH), the MCU determines
whether to access the SFRs or RAM by the type of instruction given. If it is indirect, then RAM is
accessed. If it is direct, then an SFR is accessed. See the examples below.
Table 3: SFCF Values Under Different Reset Conditions
SC11
1. P = Programmed (Bit logic state = 0),
U = Unprogrammed (Bit logic state = 1)
SC01
State of SFCF[1:0] after:
Power-on
or
External
Reset
WDT Reset
or
Brown-out
Reset
Software
Reset
U (1)
00
(default)
x0
10
U (1)
P (0)
01
x1
11
P (0)
U (1)
10
P (0)
11
T0-0.0 25087
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