參數(shù)資料
型號: SST89V54RD-33-C-PIE
廠商: Microchip Technology
文件頁數(shù): 47/92頁
文件大小: 0K
描述: IC MCU 8BIT 24KB FLASH 40PDIP
標(biāo)準(zhǔn)包裝: 9
系列: FlashFlex®
核心處理器: 8051
芯體尺寸: 8-位
速度: 33MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 8K x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
2011 Silicon Storage Technology, Inc.
DS25087A
10/11
51
FlashFlex MCU
SST89V54RD2/RD / SST89V58RD2/RD
Not Recommended for New Designs
A Microchip Technology Company
Serial Peripheral Interface
SPI Features
Master or slave operation
10 MHz bit frequency (max)
LSB first or MSB first data transfer
Four programmable bit rates
End of transmission (SPIF)
Write collision flag protection (WCOL)
Wake up from idle mode (slave mode only)
SPI Description
The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the
SST89V5xRDx and peripheral devices or between several SST89V5xRDx devices.
Figure 20 shows the correspondence between master and slave SPI devices. The SCK pin is the clock
output and input for the master and slave modes, respectively. The SPI clock generator will start follow-
ing a write to the master devices SPI data register. The written data is then shifted out of the MOSI pin
on the master device into the MOSI pin of the slave device. Following a complete transmission of one
byte of data, the SPI clock generator is stopped and the SPIF flag is set. An SPI interrupt request will
be generated if the SPI Interrupt Enable bit (SPIE) and the Serial Port Interrupt Enable bit (ES) are
both set.
An external master drives the Slave Select input pin, SS#/P1[4], low to select the SPI module as a
slave. If SS#/P1[4] has not been driven low, then the slave SPI unit is not active and the MOSI/P1[5]
port can also be used as an input port pin.
CPHA and CPOL control the phase and polarity of the SPI clock. Figures 21 and 22 show the four pos-
sible combinations of these two bits.
Figure 20:SPI Master-slave Interconnection
1255 F19.0
8-bit Shift Register
MSB Master LSB
SPI
Clock Generator
MISO MISO
MOSI MOSI
SCK
SS#
8-bit Shift Register
MSB Slave LSB
VSS
VDD
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