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參數(shù)資料
| 型號： | ST16 |
| 廠商： | 意法半導體 |
| 英文描述： | CHIP SET INTERFACE SPECIFICATION |
| 中文描述： | 芯片組接口規(guī)范 |
| 文件頁數(shù)： | 13/21頁 |
| 文件大小： | 146K |
| 代理商： | ST16 |
7/15
FSD_CHIPSET_B/0104VP2
ST16-19RFRDCS
1.6 REGISTERS MAPPING
1.6.1 Control Registers
The control bits mapping is given by the following table:
Table 2
: Control register description
Example:
Register " Reception Control ": MSB LSB
01000011
bit [7:6] "01": identification of the Register " Reception Control "
bit [5:4] "00": set to ’0’
bit [3:2] "00": speed 106K
bit 1
’1’ : automatic speed detection
bit 0
’1’ : external valid
“Address
"Description
"00”
Functionality Mode Setting
bit 0:
Cfg_Irq_Pulse
bit 1:
Cfg_Irq_High
bit 2:
Cfg_Loopback
bit 3:
ST Reserved => set to '0'
bit 4:
ST Reserved => set to '0
bit 5:
ST Reserved => set to '0'
bit [7:6]:
Register Address Bits => set to "00"
Reception Control
bit 0:
Rx_Valid_Ext
bit 1:
Rx_Speed_Auto
bit [3:2]:
Rx_Speed_Config
bit 4:
ST Reserved => set to ’0’
bit 5:
ST Reserved => set to ’0’
bit [7:6]:
Register Address Bits => set to "01"
Register 1 Transmission Control
bit [1:0]:
Tx_Speed_Config
bit[4:2]:
Tx_Egt_Config
bit 5:
ST Reserved => set to ’0’
bit [7:6]:
Register Address Bits => set to "10"
Register 2 Transmission Control
bit 0:
Tx_CRC_Disable
bit 1:
Tx_SOF_0_11
bit 2:
Tx_SOF_1_3
bit 3:
Tx_EOF_0_11
bit 4:
ST Reserved => set to '0'
bit 5:
ST Reserved => set to '0'
bit [7:6]:
Register Address Bits => set to "11"
'0'
= Toggle Mode
'0'
= Pulse Activ Low
’0’
= Usual Functionality
’1’ = Pulse Mode
‘1' = Pulse Activ High
‘1' = Loop back
"01”
’0’ = Digital Detection
’0’ = By Rx_Speed_Config Bits
"00" = 106K
’1’ = External Valid
’1’ = Automatic
"10" & "11" = 424K
"01" = 212K
"10”
"
00" = 106K
Number of d’EGT bits
"01" = 212K
"10" & "11" = 424K
“11”
'0' = CRC automatic
'0' = SOF of 10 bits at ‘0’
'0' = SOF of 2 bits at '1'
'0' = EOF of 10 bits at '0'
‘1' = CRC disable
’1' = SOF of 11 bits at ‘0’
'1' = SOF of 3 bits at '1'
'1' = EOF of 11 bits at '0'
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