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參數(shù)資料
| 型號： | ST16 |
| 廠商： | 意法半導體 |
| 英文描述： | CHIP SET INTERFACE SPECIFICATION |
| 中文描述： | 芯片組接口規(guī)范 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 146K |
| 代理商： | ST16 |
1/15
This is a Preliminary Data on a new product now in development or undergoing evaluation. Details are subject to change with-
out noctice.
PRELIMINARY DATA
ST16-19RFRDCS
CHIP SET INTERFACE SPECIFICATION
1 FPGA & MCU INTERFACE
1.1 DESCRIPTION
The goal of this document is to provide a Hardware / Software interface specifications of the FPGA com-
ponent (Xilinx SPARTANXL XCS40XL-4PQ208C) used in the STMicroelectronics Contactless System.
The FPGA manages the communication between the MCU and the Analog Front End. This component
formats the frames in accordance with ISO 14443 type B standard.
1.2 PHYSICAL INTERFACE BETWEEN FPGA AND MCU
This corresponds to a classical memory interface between bidirectional Data bus, Selection signal, Read/
Write signal and a signal used to select either FIFOs or Control/Status registers access
1.2.1 Interface signals description
In order to simplify interface specification, the FPGA logic has been designed with the same accesses for
FIFOs and Control Registers. This is the reason why the read access chronogram show only one access
type (figure 1)
However, for write access chronogram, two access types are shown (figures 2 & 3).
MCU accesses are done in burst mode for the FIFOs, it is not useful to generate addresses. So, there is
no address bus for the MCU Interface. To address the different control registers, the two MSB bits from
the data bus must be used.
These control registers have to be setted during the first transmission each time the code is down loaded
in FPGA (start up of the reader) or when any parameter has to be modified. For later transmissions, the
control registers don’t need to be re initialised.
The control Register Description is available in table 2.
FSD_CHIPSET_B/0104VP2
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