參數(shù)資料
型號(hào)： ST16C452IJ68PS-F
廠商： Exar Corporation
文件頁數(shù)： 9/30頁
文件大小： 0K
描述： IC UART W/PAR PORT DUAL 68PLCC
標(biāo)準(zhǔn)包裝： 19
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 1 字節(jié)
規(guī)程： 打印機(jī)
電源電壓： 2.97 V ~ 5.5 V
帶并行端口： 是
帶故障啟動(dòng)位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 68-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 68-PLCC
包裝： 管件
17
ST16C452/452PS
Rev. 3.20
LCR
Parity selection
Bit-5
Bit-4
Bit-3
X
0
No parity
0
1
Odd parity
0
1
Even parity
1
0
1
Force parity odd parity
1
Forced even parity
LCR BIT-6:
When enabled the Break control bit causes a break
condition to be transmitted (the TX output is forced to
a logic 0 state). This condition exists until disabled by
setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition. (normal default
condition)
Logic 1 = Forces the transmitter output (TX) to a logic
0 for alerting the remote receiver to a line break
condition.
LCR BIT-7:
The internal baud rate counter latch and Enhance
Feature mode enable.
Logic 0 = Divisor latch disabled. (normal default
condition)
Logic 1 = Divisor latch and enhanced feature register
enabled.
Modem Control Register (MCR)
This register controls the interface with the modem or
a peripheral device.
MCR BIT-0:
Logic 0 = Force -DTR output to a logic 1. (normal
default condition)
Logic 1 = Force -DTR output to a logic 0.
MCR BIT-1:
Logic 0 = Force -RTS output to a logic 1. (normal
default condition)
Logic 1 = Force -RTS output to a logic 0.
MCR BIT-2:
This bit is used in the Loop-back mode only. In the
loop-back mode this bit is use to write the state of the
modem -RI interface signal.
MCR BIT-3: (Used to control the modem -CD signal
in the loop-back mode.)
Logic 0 = Forces INT (A-B) outputs to the three state
mode. (normal default condition) In the Loop-back
mode, sets -CD internally to a logic 1.
Logic 1 = Forces the INT (A-B) outputs to the active
mode. In the Loop-back mode, sets -CD internally to
a logic 0.
MCR BIT-4:
Logic 0 = Disable loop-back mode. (normal default
condition)
Logic 1 = Enable local loop-back mode (diagnostics).
MCR BIT 5-7:
Not Used - initialized to a logic 0.
Line Status Register (LSR)
This register provides the status of data transfers
between. the 452/452PS and the CPU.
LSR BIT-0:
Logic 0 = No data in receive holding register. (normal
default condition)
Logic 1 = Data has been received and is saved in the
receive holding register.
LSR BIT-1:
Logic 0 = No overrun error. (normal default condition)
Logic 1 = Overrun error. A data overrun error occurred
in the receive shift register. This happens when addi-
tional data arrives while the RHR is full. In this case the
previous data in the shift register is overwritten. Note
that under this condition the data byte in the receive
shift register is not transferred into the RHR, therefore
the data in the RHR is not corrupted by the error.
LSR BIT-2:
Logic 0 = No parity error. (normal default condition)
Logic 1 = Parity error. The receive character does not
have correct parity information and is suspect.
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