參數(shù)資料
型號(hào)： ST16C550IQ48-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 11/35頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 16B SGL 48TQFP
標(biāo)準(zhǔn)包裝： 250
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
電源電壓： 2.97 V ~ 5.5 V
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
其它名稱： 1016-1262
ST16C550
19
Rev. 5.01
this bit causes the UART to issue an interrupt to CPU
when the THR interrupt enable is set. The THR bit is
set to a logic 1 when a character is transferred from
the transmit holding register into the transmitter shift
register. The bit is reset to logic 0 concurrently with
the loading of the transmitter holding register by the
CPU. In the FIFO mode this bit is set when the transmit
FIFO is empty; it is cleared when at least 1 byte is
written to the transmit FIFO.
LSR BIT-6:
This bit is the Transmit Empty indicator. This bit is set
to a logic 1 whenever the transmit holding register and
the transmit shift register are both empty. It is reset to
logic 0 whenever either the THR or TSR contains a
data character. In the FIFO mode this bit is set to one
whenever the transmit FIFO and transmit shift register
are both empty.
LSR BIT-7:
Logic 0 = No Error (normal default condition)
Logic 1 = At least one parity error, framing error or
break indication is in the current FIFO data. This bit is
cleared when there are no remaining LSR errors in the
RX FIFO.
Modem Status Register (MSR)
This register provides the current state of the control
interface signals from the modem, or other peripheral
device that the ST16C550 is connected to. Four bits
of this register are used to indicate the changed
information. These bits are set to a logic 1 whenever
a control input from the modem changes state. These
bits are set to a logic 0 whenever the CPU reads this
register.
MSR BIT-0:
Logic 0 = No -CTS Change (normal default condition)
Logic 1 = The -CTS input to the ST16C550 has
changed state since the last time it was read. A
modem Status Interrupt will be generated.
MSR BIT-1:
Logic 0 = No -DSR Change (normal default condition)
Logic 1 = The -DSR input to the ST16C550 has
changed state since the last time it was read. A
modem Status Interrupt will be generated.
MSR BIT-2:
Logic 0 = No -RI Change (normal default condition)
Logic 1 = The -RI input to the ST16C550 has changed
from a logic 0 to a logic 1. A modem Status Interrupt
will be generated.
MSR BIT-3:
Logic 0 = No -CD Change (normal default condition)
Logic 1 = Indicates that the -CD input to the has
changed state since the last time it was read. A
modem Status Interrupt will be generated.
MSR BIT-4:
CTS (active high, logical 1). Normally this bit is the
compliment of the -CTS input. In the loop-back mode,
this bit is equivalent to the RTS bit in the MCR register.
MSR BIT-5:
DSR (active high, logical 1). Normally this bit is the
compliment of the -DSR input. In the loop-back mode,
this bit is equivalent to the DTR bit in the MCR register.
MSR BIT-6:
RI (active high, logical 1). Normally this bit is the
compliment of the -RI input. In the loop-back mode
this bit is equivalent to the OP1 bit in the MCR register.
MSR BIT-7:
CD (active high, logical 1). Normally this bit is the
compliment of the -CD input. In the loop-back mode
this bit is equivalent to the OP2 bit in the MCR register.
Scratchpad Register (SPR)
The ST16C550 provides a temporary data register to
store 8 bits of user information.
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