A=0° - 70°C (-40° - +85°C for Industrial grade packages)" />
參數(shù)資料
型號: ST16C550IQ48-F
廠商: Exar Corporation
文件頁數(shù): 14/35頁
文件大?。?/td> 0K
描述: IC UART FIFO 16B SGL 48TQFP
標(biāo)準(zhǔn)包裝: 250
特點(diǎn): *
通道數(shù): 1,UART
FIFO's: 16 字節(jié)
電源電壓: 2.97 V ~ 5.5 V
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
其它名稱: 1016-1262
ST16C550
21
Rev. 5.01
AC ELECTRICAL CHARACTERISTICS
T
A=0° - 70°C (-40° - +85°C for Industrial grade packages),
Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.
T
1w,T2w
Clock pulse duration
17
ns
T
3w
Oscillator/Clock frequency
16
24
MHz
T4w
Address strobe width
35
25
ns
T5s
Address setup time
5
0
ns
T5h
Address hold time
5
ns
T
6s
Chip select setup time
5
0
ns
T6h
Chip select hold time
0
ns
T
6s'
Address setup time
10
5
ns
see Note 1
T
7d
-IOR delay from chip select
10
ns
T
7w
-IOR strobe width
77
38
ns
T
7w'
Chip select width
77
38
ns
T
7h
Chip select hold time from -IOR
0
ns
T
7h'
Address hold time
5
ns
see Note 1
T
8d
-IOR delay from address
10
ns
T
9d
Read cycle delay
77
38
ns
T
11d
-IOR to -DDIS delay
15
10
ns
100 pF load
T
12d
Delay from -IOR to data
35
25
ns
T
12h
Data disable time
25
15
ns
T
13d
-IOW delay from chip select
10
ns
T
13w
-IOW strobe width
27
15
ns
T
13w'
Chip select width
77
38
ns
T
13h
Chip select hold time from -IOW
0
ns
T
14d
-IOW delay from address
10
ns
T
15d
Write cycle delay
77
38
ns
T
16s
Data setup time
20
15
ns
T
16h
Data hold time
5
ns
T
17d
Delay from -IOW to output
50
40
ns
100 pF load
T
18d
Delay to set interrupt from MODEM input
40
35
ns
100 pF load
T
19d
Delay to reset interrupt from -IOR
40
35
ns
100 pF load
T
20d
Delay from stop to set interrupt
1
Rclk
T
21d
Delay from -IOR to reset interrupt
45
40
ns
100 pF load
T
22d
Delay from stop to interrupt
45
40
ns
T
23d
Delay from initial INT reset to transmit
8
24
8
24
Rclk
start
T
24d
Delay from -IOW to reset interrupt
45
40
ns
T
25d
Delay from stop to set -RxRdy
1
Rclk
T
26d
Delay from -IOR to reset -RxRdy
45
40
ns
T
27d
Delay from -IOW to set -TxRdy
45
40
ns
T
28d
Delay from start to reset -TxRdy
8
Rclk
T
R
Reset pulse width
40
ns
N
Baud rate divisor
1
216-1
1
216-1
Rclk
Note 1: Applicable only when -AS is tied low.
Symbol
Parameter
Limits
Units Conditions
3.3
5.0
Min
Max Min
Max
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