參數(shù)資料
型號(hào): ST16C550IQ48TR-F
廠商: Exar Corporation
文件頁數(shù): 5/35頁
文件大?。?/td> 0K
描述: IC UART FIFO 16B SGL 48TQFP
標(biāo)準(zhǔn)包裝: 1,500
特點(diǎn): *
通道數(shù): 1,UART
FIFO's: 16 字節(jié)
電源電壓: 2.97 V ~ 5.5 V
帶故障啟動(dòng)位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 帶卷 (TR)
ST16C550
13
Rev. 5.01
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the twelve ST16C550 internal registers. The assigned
bit functions are more fully defined in the following paragraphs.
Table 4, ST16C550 INTERNAL REGISTERS
A2 A1 A0
Register
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
[Default]
Note *2
General Register Set
0
RHR [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
THR [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
1
IER [00]
0000
modem
receive
transmit
receive
status
line
holding
interrupt
status
register
interrupt
0
1
0
FCR [00]
RCVR
0
DMA
XMIT
RCVR
FIFO
trigger
mode
FIFO
enable
(MSB)
(LSB)
select
reset
0
1
0
ISR [01]
FIFO’s
0
INT
enabled
priority
status
bit-2
bit-1
bit-0
0
1
LCR [00]
divisor
set
even
parity
stop
word
latch
break
parity
enable
bits
length
enable
bit-1
bit-0
1
0
MCR [00]
0
loopback
-OP2
-OP1
-RTS
-DTR
enable
1
0
1
LSR [60]
FIFO
trans.
break
framing
parity
overrun
receive
data
empty
holding
interrupt
error
data
error
empty
ready
1
0
MSR [X0]
CD
RI
DSR
CTS
delta
-CD
-RI
-DSR
-CTS
1
SPR [FF]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
Baud Rate Generator Divisor Registers. Accessible when LCR bit-7 is set to logic 1. Note 1*
0
DLL [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
1
DLM [XX]
bit-15
bit-14
bit-13
bit-12
bit-11
bit-10
bit-9
bit-8
Note *1: The BRG registers are accessible only when LCR bit-7 is set to a logic 1.
Note *2: The value represents the register’s initialized HEX value. An “X” signifies a 4-bit un-initialized nibble.
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