ST16C554/554D
27
REV. 4.0.1
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
AC ELECTRICAL CHARACTERISTICS
TA = 0
O TO +70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97 TO 5.5V, 70 PF LOAD WHERE
APPLICABLE
SYMBOL
PARAMETER
LIMITS
3.3V ± 10%
MIN
MAX
LIMITS
5V ± 10%
MIN
MAX
UNIT
CLK
External Clock Low/High Time
63
21
ns
OSC
UART Crystal/External Clock Frequency
8
24
MHz
TAS
Address Setup Time (16 Mode)
5
0
ns
TAH
Address Hold Time (16 Mode)
5
ns
TCS
Chip Select Width (16 Mode)
80
50
ns
TRD
IOR# Strobe Width (16 Mode)
80
50
ns
TDY
Read Cycle Delay (16 Mode)
40
30
ns
TRDV
Data Access Time (16 Mode)
40
25
ns
TDD
Data Disable Time (16 Mode)
25
15
ns
TWR
IOW# Strobe Width (16 Mode)
35
25
ns
TDY
Write Cycle Delay (16 Mode)
40
30
ns
TDS
Data Setup Time (16 Mode)
20
15
ns
TDH
Data Hold Time (16 Mode)
5
ns
TADS
Address Setup (68 Mode)
10
ns
TADH
Address Hold (68 Mode)
15
ns
TRWS
R/W# Setup to CS# (68 Mode)
10
ns
TRDA
Data Access Time (68 mode)
40
25
ns
TRDH
Data Disable Time (68 mode)
25
15
ns
TWDS
Write Data Setup (68 mode)
20
15
ns
TWDH
Write Data Hold (68 Mode)
10
ns
TRWH
CS# De-asserted to R/W# De-asserted (68 Mode)
10
ns
TCSL
CS# Strobe Width (68 Mode)
80
50
ns
TCSD
CS# Cycle Delay (68 Mode)
40
30
ns
TWDO
Delay From IOW# To Output
50
40
ns
TMOD
Delay To Set Interrupt From MODEM Input
40
35
ns
TRSI
Delay To Reset Interrupt From IOR#
40
35
ns
TSSI
Delay From Stop To Set Interrupt
1
Bclk