- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3766 > ST16C554DIQ64-F (Exar Corporation)IC UART FIFO 16B QUAD 64LQFP PDF資料下載
參數(shù)資料
| 型號： | ST16C554DIQ64-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 10/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 16B QUAD 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 特點： | * |
| 通道數(shù)： | 4，QUART |
| FIFO's： | 16 字節(jié) |
| 規(guī)程： | RS232 |
| 電源電壓： | 2.97 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1268 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁
ST16C554/554D
18
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
REV. 4.0.1
4.4
Interrupt Status Register (ISR)
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 9, shows the data values (bit 0-3) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.4.1
Interrupt Generation:
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by THR empty (non-FIFO mode) or TX FIFO empty (FIFO mode).
MSR is by any of the MSR bits 0, 1, 2 and 3.
4.4.2
Interrupt Clearing:
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or by writing to THR.
MSR interrupt is cleared by a read to the MSR register.
]
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 9).
ISR[5:4]: Reserved (Default 0)
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-3
BIT-2
BIT-1
BIT-0
1
0
1
0
LSR (Receiver Line Status Register)
2
1
0
RXRDY (Receive Data Time-out)
3
0
1
0
RXRDY (Received Data Ready)
4
0
1
0
TXRDY (Transmit Empty)
5
0
MSR (Modem Status Register)
-
0
1
None (default)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR16V554IV80-F | IC UART FIFO 16B QUAD 80LQFP |
| XR16V554DIV-F | IC UART FIFO 16B QUAD 64LQFP |
| ST16C554DCQ64-F | IC UART FIFO 16B QUAD 64LQFP |
| ATMEGA164A-AUR | IC MCU AVR 16K 20MHZ 44TQFP |
| ATMEGA164A-MUR | IC MCU AVR 16K 20MHZ 44VQFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C554DIQ64TR-F | 功能描述:UART 接口集成電路 QUAD UART W/16 BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C554ECQ64 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| ST16C554EDCJ68 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| ST16C554EDCQ64 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| ST16C554EDIJ68 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。