REV. 5.0.2 8 1.0 PRODUCT DESCRIPTION The ST16C654 (654) integrates the functions of " />
參數(shù)資料
型號： ST16C654CQ64TR-F
廠商： Exar Corporation
文件頁數(shù)： 50/51頁
文件大?。?/td> 0K
描述： IC UART FIFO 64B QUAD 64LQFP
標(biāo)準(zhǔn)包裝： 1,000
特點(diǎn)： *
通道數(shù)： 4，QUART
FIFO's： 64 字節(jié)
規(guī)程： RS232
電源電壓： 2.97 V ~ 5.5 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 帶卷 (TR)
ST16C654/654D
xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.2
8
1.0 PRODUCT DESCRIPTION
The ST16C654 (654) integrates the functions of 4 enhanced 16C550 Universal Asynchrounous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.
Additionally, each UART channel has 64-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware
flow control, automatic Xon/Xoff and special character software flow control, infrared encoder and decoder
(IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 1.5
Mbps. The ST16C654 can operate from 2.97 to 5.5 volts. The 654 is fabricated with an advanced CMOS
process.
Enhanced FIFO
The 654 QUART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of
16 bytes in the ST16C554, or one byte in the ST16C454. The 654 is designed to work with high performance
data communication systems, that require fast data processing time. Increased performance is realized in the
654 by the larger transmit and receive FIFOs, FIFO trigger level control and automatic flow control mechanism.
This allows the external processor to handle more networking tasks within a given time. For example, the
ST16C554 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses a character
length of 11 bits, including start/stop bits at 115.2Kbps). This means the external CPU will have to service the
receive FIFO at 1.53 ms intervals. However with the 64 byte FIFO in the 654, the data buffer will not require
unloading/loading for 6.1 ms. This increases the service interval giving the external CPU additional time for
other applications and reducing the overall UART interrupt servicing time. In addition, the programmable FIFO
level trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data
throughput performance especially when operating in a multi-channel system. The combination of the above
greatly reduces the CPU’s bandwidth requirement, increases performance, and reduces power consumption.
Data Rate
The 654 is capable of operation up to 1.5 Mbps at 5V with 16x internal sampling clock rate. The device can
operate at 5V with a crystal oscillator of up to 24 MHz crystal on pins XTAL1 and XTAL2, or external clock
source of 24 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz and through a software option, the user
can set the prescaler bit for data rates of up to 921.6 kbps.
Enhanced Features
The rich feature set of the 654 is available through the internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger levels, selectable baud rates, infrared encoder/decoder
interface, modem interface controls, and a sleep mode are all standard features. MCR bit-5 provides a facility
for turning off (Xon) software flow control with any incoming (RX) character. In the 16 mode INTSEL and MCR
bit-3 can be configured to provide a software controlled or continuous interrupt capability. Due to pin limitations
for the 64 pin 654 this feature is offered by two different LQFP packages. The ST16C654DCV operates in the
continuous interrupt enable mode by internally bonding INTSEL to VCC. The ST16C654CV operates in
conjunction with MCR bit-3 by internally bonding INTSEL to GND.
The ST16C654 offers a clock prescaler select pin to allow system/board designers to preset the default baud
rate table on power up. The CLKSEL pin selects the div-by-1 or div-by-4 prescaler for the baud rate generator.
It can then be overridden following initialization by MCR bit-7.
The 100 pin packages offer several other enhanced features. These features include a CHCCLK clock input,
FSTAT register and separate IrDA TX outputs. The CHCCLK must be connected to the XTAL2 pin for normal
operation or to external MIDI (Music Instrument Digital Interface) oscillator for MIDI applications. A separate
register (FSTAT) is provided for monitoring the real time status of the FIFO signals TXRDY# and RXRDY# for
each of the four UART channels (A-D). This reduces polling time involved in accessing individual channels.
The 100 pin QFP package also offers four separate IrDA (Infrared Data Association Standard) TX outputs for
Infrared applications. These outputs are provided in addition to the standard asynchronous modem data
outputs.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST16C654D 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
ST16C654DCQ64 制造商:Exar Corporation 功能描述:
ST16C654DCQ64-0A-EB 功能描述:界面開發(fā)工具 Supports C654D 64 ld TQFP, ISA Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
ST16C654DCQ64-F 功能描述:UART 接口集成電路 QUAD UARTW/64BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
ST16C654DCQ64-F 制造商:Exar Corporation 功能描述:IC QUAD UART 1.5MBPS 5.5V 64-LQFP
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