REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO 43 FIGURE " />
參數(shù)資料
型號: ST16C654DIQ64-F
廠商: Exar Corporation
文件頁數(shù): 38/51頁
文件大小: 0K
描述: IC UART FIFO 64B QUAD 64LQFP
標(biāo)準(zhǔn)包裝: 160
特點: *
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
規(guī)程: RS232
電源電壓: 2.97 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
其它名稱: 1016-1271
xr
ST16C654/654D
REV. 5.0.2
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
43
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A-D
TX
TXRDY#
IOW#
INT*
D0:D7
Start
Bit
D0:D7
Stop
Bit
D0:D7
T
WT
TXNonFIFO
T
WT
T
WT
T
WRI
T
WRI
T
WRI
T
SRT
T
SRT
T
SRT
*INT is cleared when the ISR is read or when data is loaded into the THR.
ISR is read
(Loading data
into THR)
(Unloading)
IER[1]
enabled
RX
RXRDY#
IOR#
INT
D0:D7
S
T
SSR
RXINTDMA#
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
First Byte is
Received in
RX FIFO
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
RR
T
RRI
T
SSI
(Reading data out
of RX FIFO)
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