參數(shù)資料
型號: ST6228CN6
廠商: 意法半導體
英文描述: ER 5C 5#16S PIN RECP WALL
中文描述: 8位單片機與微控制器/ D轉換器,自動重加載定時器,UART的秘書長辦公室,安全復位和28引腳封裝
文件頁數(shù): 47/84頁
文件大?。?/td> 561K
代理商: ST6228CN6
47/84
47
ST62T28C/E28C
AUTO-RELOAD TIMER
(Cont’d)
Capture Mode with PWM Generation
. In this
mode, the AR counter operates as a free running
8-bit counter fed by the prescaler output. The
counter is incremented on every clock rising edge.
An 8-bit capture operation from the counter to the
ARRC register is performed on every active edge
on the ARTIMin pin, when enabled by Edge Con-
trol bits SL0, SL1 in the ARSC1 register. At the
same time, the External Flag, EF, in the ARSC0
register is set and an external interrupt request is
generated if the External Interrupt Enable bit, EIE,
in the ARMC register, is set. The EF flag must be
reset by user software.
Each ARTC overflow sets ARTIMout, while a
match between the counter and ARCP (Compare
Register) resets ARTIMout and sets the compare
flag, CPF. A compare interrupt request is generat-
ed if the related compare interrupt enable bit,
CPIE, is set. A PWM signal is generated on ARTI-
Mout. The CPF flag must be reset by user soft-
ware.
The frequency of the generated signal is deter-
mined by the prescaler setting. The duty cycle is
determined by the ARCP register.
Initialization and reading of the counter are identi-
cal to the auto-reload mode (see previous descrip-
tion).
Enabling and selection of clock sources is control-
led bythe CC0and CC1 bits inthe ARStatus Con-
trol Register, ARSC1.
The prescaler division ratio is selected by pro-
gramming the PS0, PS1 and PS2 bits in the
ARSC1 Register.
In Capture mode, the allowed clock sources are
the internal clock and the internal clock divided by
3; the external ARTIMin input pin should not be
used as a clock source.
Capture Mode with Reset of counter and pres-
caler, and PWM Generation.
This mode is identi-
cal to the previous one, with the difference that a
capture condition also resets the counter and the
prescaler, thus allowing easy measurement of the
time between two captures (for input period meas-
urement on the ARTIMin pin).
Load on External Input
. Thecounter operates as
a free running 8-bit counter fed by the prescaler.
the count is incremented on every clock rising
edge.
Each counter overflow sets the ARTIMout pin. A
match between the counter and ARCP (Compare
Register) resets the ARTIMout pin and sets the
compare flag, CPF. A compare interrupt request is
generated if the related compare interrupt enable
bit, CPIE, is set. A PWM signal is generated on
ARTIMout. The CPF flag must be reset by user
software.
Initialization of the counter is as described in the
previous paragraph. In addition, ifthe externalAR-
TIMin input is enabled,an active edge onthe input
pin will copythe contents of the ARRC register into
the counter, whether the counter is running or not.
Notes
:
The allowed AR Timer clock sources are the fol-
lowing:
The clock frequency should not be modified while
the counter is counting, since the counter may be
set to an unpredictable value. For instance, the
multiplexer setting should not be modified while
the counter is counting.
Loading of the counter by any means (by auto-re-
load, through ARLR, ARRC or by the Core) resets
the prescaler at the same time.
Care should be taken when both the Capture inter-
rupt and the Overflow interrupt are used. Capture
and overflow are asynchronous. If the capture oc-
curs when the Overflow Interrupt Flag, OVF, is
high (between counter overflow and the flag being
reset by software, in the interrupt routine), the Ex-
ternal Interrupt Flag, EF, may be cleared simul-
taneusly without the interrupt being taken into ac-
count.
The solution consists in resetting the OVF flag by
writing 06h in the ARSC0 register. The value of EF
is not affected by this operation. If an interrupt has
occured, it will be processed when the MCU exits
from the interrupt routine (the second interrupt is
latched).
AR Timer Mode
Auto-reload mode
Capture mode
Capture/Reset mode
External Load mode
Clock Sources
f
INT
, f
INT/3
, ARTIMin
f
INT
, f
INT/3
f
INT
, f
INT/3
f
INT
, f
INT/3
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