參數(shù)資料
型號： ST62T03CM6E
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDSO16
封裝： 0.300 INCH, LEAD FREE, PLASTIC, SOP-16
文件頁數(shù)： 17/100頁
文件大?。?/td> 1440K
代理商： ST62T03CM6E
ST6200C/ST6201C/ST6203C
23/100
6.1 RESET
6.1.1 Introduction
The MCU can be reset in three ways:
s
A low pulse input on the RESET pin
s
Internal Watchdog reset
s
Internal Low Voltage Detector (LVD) reset
6.1.2 RESET Sequence
The basic RESET sequence consists of 3 main
phases:
s
Internal (watchdog or LVD) or external Reset
event
s
A delay of 2048 clock (fINT) cycles
s
RESET vector fetch
The reset delay allows the oscillator to stabilise
and ensures that recovery has taken place from
the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
When a reset occurs:
– The stack is cleared
– The PC is loaded with the address of the Reset
vector. It is located in program ROM starting at
address 0FFEh.
A jump to the beginning of the user program must
be coded at this address.
– The interrupt flag is automatically set, so that the
CPU is in Non Maskable Interrupt mode. This
prevents the initialization routine from being in-
terrupted. The initialization routine should there-
fore be terminated by a RETI instruction, in order
to go back to normal mode.
Figure 13. RESET Sequence
VDD
RESET PIN
WATCHDOG
VIT+
VIT-
WATCHDOG UNDERFLOW
RESET
2048 CLOCK CYCLE (fINT) DELAY
LVD
RESET
INTERNAL
RUN
RESET
RUN
RESET
1
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