參數(shù)資料
型號： ST6399
廠商： 意法半導(dǎo)體
英文描述： MOSFET; Transistor Polarity:P Channel; Drain Source Voltage, Vds:-30V; Continuous Drain Current, Id:-4.1A; On-Resistance, Rds(on):0.08ohm; Rds(on) Test Voltage, Vgs:-10V; Package/Case:8-1206; Leaded Process Compatible:No
中文描述： 8位微控制器HCMOS電視頻率合成帶OSD
文件頁數(shù)： 19/68頁
文件大?。?/td> 560K
代理商： ST6399
DRBR
Data RAM
Bank Register
(E8h, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
DRBR0
DRBR1
DRBR2
DRBR3
DRBR4
DRBR5
DRBR6
DRBR7
Figure18. Data RAM Bank Register
MEMORY SPACES
(Continued)
Data RAM/EEPROM/OSDRAM Addressing
In all membersoftheST639xfamily64bytesofdata
RAMaredirectlyaddressableinthe dataspacefrom
80h to BFh addresses.The additional192 bytes of
RAM, the 384 bytes of EEPROM , and the OSD
RAM can be addressed using the banks of 64
bytes located between addresses 00h and 3Fh.
The selectionof the bank is done by programming
the Data RAM Bank Register (DRBR) located at
the E8h address of the Data Space. In this way
each bankof RAM,EEPROMorOSDRAMcan se-
lect 64 bytes at a time. No more than one bank
should beset at atime.
DRBR Value
Selection
Hex.
Binary
01h
0000 0001
EEPROMPage 0
All devices
02h
0000 0010
EEPROMPage 1
03h
0000 0011
EEPROMPage 2
ST6395 and ST6397
ONLY
81h
1000 0001
EEPROMPage 3
82h
1000 0010
EEPROMPage 4
83h
1000 0011
EEPROMPage 5
04h
0000 0100
RAM Page 2
All devices
08h
0000 1000
RAM Page 3
10h
0001 0000
RAM Page 4
20h
0010 0000
OSD Page 5
40h
0100 0000
OSD Page 6
Table 5. Data RAM Bank Register Set-up
DRBR7,DRBR1,DRBR0.
These bits select the
EEPROM pages.
DRBR6, DRBR5.
Each of thesebits, when set, will
select one OSD RAM registerpage.
DRBR4,DRBR3,DRBR2.
Eachofthesebits,when
set, will select one RAM page.
This registeris undefined afterreset.
Table 5 summarizes how to set the Data RAM
Bank Registerin orderto select the various banks
or pages.
Note :
Care is required when handling the DRBR as it is
write only. For this reason, it is not allowed to
change the DRBR contentswhile executing inter-
rupts drivers, as the driver cannot save and than
restore its previous content. If it is impossible to
avoid the writing of this register in interrupts driv-
ers, an image of this register must be saved in a
RAM location, and each time the program writes
the DRBRit writes alsothe image register.
The image registermust be written first, soif an in-
terrupt occurs between the two instructions the
DRBR is not affected.
ST6391,92,93,95,97,99
15/64
相關(guān)PDF資料
PDF描述
ST63P06 8-BIT HCMOS PIGGYBACK MCUs FOR TV APPLICATIONS
ST63P07 8-BIT HCMOS PIGGYBACK MCUs FOR TV APPLICATIONS
ST63P08 MOSFET; Drain Source Voltage, Vds:-20V; Continuous Drain Current, Id:-3.9A; On-Resistance, Rds(on):0.055ohm; Rds(on) Test Voltage, Vgs:-4.5V; Leaded Process Compatible:Yes; Mounting Type:Surface Mount; Package/Case:8-1206 RoHS Compliant: Yes
ST63P16 MOSFET; Transistor Polarity:P Channel; Drain Source Voltage, Vds:-8V; Continuous Drain Current, Id:5.2A; On-Resistance, Rds(on):0.035ohm; Rds(on) Test Voltage, Vgs:-4.5V; Package/Case:8-1206; Leaded Process Compatible:No RoHS Compliant: No
ST63P17 8-BIT HCMOS PIGGYBACK MCUs FOR TV APPLICATIONS
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