參數(shù)資料
型號(hào)： ST6399
廠商： 意法半導(dǎo)體
英文描述： MOSFET; Transistor Polarity:P Channel; Drain Source Voltage, Vds:-30V; Continuous Drain Current, Id:-4.1A; On-Resistance, Rds(on):0.08ohm; Rds(on) Test Voltage, Vgs:-10V; Package/Case:8-1206; Leaded Process Compatible:No
中文描述： 8位微控制器HCMOS電視頻率合成帶OSD
文件頁數(shù)： 33/68頁
文件大小： 560K
代理商： ST6399
TIMERS
(Continued)
Figure33. Timer Working Principle
Timer OperatingModes
AsonST639xdevicesthe externalTIMER pin is not
availabletheonlyallowed operatingmodeistheout-
put mode thathaveto beselectedbysetting to 1bit
4 and by clearing to 0 bit 5 in the TSCR1 register.
Thisprocedurewill enablebothTimer1andTimer 2.
OutputMode(TSCR1 D4 = 1, TSCR1 D5= 0).
On
this mode the timer prescaler is clocked by the
prescaler clock input (OSC/12). The user can se-
lect thedesired prescaler divisionratio throughthe
PS2/PS1/PS0bits. When TCR count reaches 0, it
sets the TMZbit in the TSCR.
The TMZ bit can be tested under program control
to perform timer functions whenever it goes high.
Bit D4and D5on TSCR2 (Timer 2)registerare not
implemented.
Timer Interrupt
When thecounter register decrementsto zero and
the softwarecontrolledETI (enable timer interrupt)
bit is set to one then an interrupt request associ-
ated tointerruptvector#3(forTimer1)and tointer-
rupt vector#1 (for Timer2) is generated.When the
counter decrementsto zero also the TMZ bitin the
TSCR registeris set to one.
Notes :
TMZ is set when the counter reaches 00H ; how-
ever, it may be set bywriting 00Hin the TCR regis-
ter or setting the bit 7 of the TSCR register. TMZ
bit must be cleared by user software when servic-
ing thetimer interrupt to avoid undesired interrupts
when leavingthe interrupt serviceroutine.After re-
set,the8-bitcounterregisterisloadedto FFhwhile
the 7-bitprescaler isloaded to 7Fh, andthe TSCR
register is cleared which means that timer is
stopped (PSI=0)and timer interruptdisabled.
A write to the TCR register will predominate over
the 8-bitcounterdecrementto 00h function,i.e.if a
write and a TCR register decrement to 00h occur
simultaneously,thewritewill takeprecedence,and
the TMZ bitis notsetuntilthe 8-bitcounterreaches
00h again. The values of the TCR and the PSC
registers can be readaccuratelyat any time.
ST6391,92,93,95,97,99
29/64
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