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| 型號(hào)： | ST72141K2B3/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | 0.400 INCH, PLASTIC, SDIP-32 |
| 文件頁(yè)數(shù)： | 15/133頁(yè) |
| 文件大?。?/td> | 2615K |
| 代理商： | ST72141K2B3/XXX |
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Obsolete
Product(s)
- Obsolete
Product(s)
ST72141K2
111/133
8-BIT A/D CONVERTER (ADC) (Cont’d)
8.5.6 Register Description
CONTROL/STATUS REGISTER (CSR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = COCO Conversion Complete
This bit is set by hardware. It is cleared by soft-
ware reading the result in the DR register or writing
to the CSR register.
0: Conversion is not complete.
1: Conversion can be read from the DR register.
Bit 6 = Reserved. Must always be cleared.
Bit 5 = ADON A/D converter On
This bit is set and cleared by software.
0: A/D converter is switched off.
1: A/D converter is switched on.
Note: A typical 30 s delay time is necessary for
the ADC to stabilize when the ADON bit is set.
Bit 4 = Reserved. Forced by hardware to 0.
Bit 3 = Reserved. Must always be cleared.
Bits 2:0: CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Table 45. Channel Selection
*IMPORTANT NOTE: The number of pins AND
the channel selection vary according to the device.
REFER TO THE DEVICE PINOUT).
DATA REGISTER (DR)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:0 = AD[7:0] Analog Converted Value
This register contains the converted analog value
in the range 00h to FFh.
Reading this register resets the COCO flag.
Table 46. ADC Register Map and Reset Values
70
COCO
-
ADON
0
-
CH2
CH1
CH0
Pin*
CH2
CH1
CH0
AIN0
000
AIN1
001
AIN2
010
AIN3
011
AIN4
100
AIN5
101
AIN6
110
AIN7
111
70
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Address
(Hex.)
Register
Label
765
4321
0
0070h
ADCDR
Reset Value
IS11
0
IS10
0
MCO
0
IS21
0
IS20
0
CP1
0
CP0
0
SMS
0
0071h
ADCCSR
Standard
Reset Value
COCO
00
ADON
00
0
CH2
0
CH1
0
CH0
0
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| ST72141K2B6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH ELECTRIC-MOTOR CONTROL, ADC, 16-BIT TIMERS, SPI INTERFACE |
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