參數(shù)資料
型號(hào): ST72141K2B3/XXX
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝: 0.400 INCH, PLASTIC, SDIP-32
文件頁(yè)數(shù): 83/133頁(yè)
文件大?。?/td> 2615K
代理商: ST72141K2B3/XXX
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Obsolete
Product(s)
- Obsolete
Product(s)
ST72141K2
53/133
MOTOR CONTROLLER (Cont’d)
8.1.4.2 Delay Manager
Figure 33. Overview of MTIM Timer
This part of the MTC contains all the time-related
functions, its architecture is based on an 8-bit shift
left/shift right timer shown in Figure 33. The MTIM
timer includes:
– An auto-updated prescaler
– A capture/compare register for software demag-
netization simulation (MDREG)
– Two cascaded capture register (MZREG and
MZPRV) for storing the times between two con-
secutive BEMF zero crossings (Z events)
– An 8x8 bit multiplier for auto computing the next
commutation time
– One compare register for phase commutation
generation (MCOMP)
The MTIM timer module can work in two main
modes. In switched mode the user must process
the step duration and commutation time by soft-
ware, in autoswitched mode the commutation ac-
tion is performed automatically depending on the
rotor position information and register contents.
Table 17. Switched and Autoswitched Modes
Switched Mode
This feature allows the motor to be run step-by-
step. This is useful when the rotor speed is still too
low to generate a BEMF. It can also run other
kinds of motor without BEMF generation such as
induction motors or switch reluctance motors. This
mode can also be used for autoswitching with all
computation for the next commutation time done
by software (hardware multiplier not used) and us-
ing the powerful interrupt set of the peripheral.
In this mode, the step time is directly written by
software in the commutation compare register
MCOMP. When the MTIM timer reaches this value
a commutation occurs (C event) and the MTIM
timer is reset.
8-bit Up Counter MTIM§
MZREG [Zn]
§
MZPRV [Zn-1]
§
C
DS
MDREG [Dn]
§
Compare
MCOMP [Cn+1]
§
Z
DH
ck
C
DS,H
Z
8
Tratio
SDM bit
Z
clr
1
0
C
SWA bit
20s/C
§ = Register updated on R event
To interrupt generator
MCRA register
MCRB register
SWA
bit
Commutation Type
MCOMP User
access
0
Switched mode
Read/Write
1
Autoswitched mode
Read only
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