參數(shù)資料
型號(hào): ST72324BLK4BA/XXX
廠商: STMICROELECTRONICS
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝: 0.400 INCH, PLASTIC, SDIP-32
文件頁(yè)數(shù): 5/151頁(yè)
文件大?。?/td> 1209K
代理商: ST72324BLK4BA/XXX
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ST72F324L, ST72324BL
102/151
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.6.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by hard-
ware when software reads the ADCDRH register
or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software.
0: fADC = fCPU/4
1: fADC = fCPU/2
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
Bit 4 = Reserved. Must be kept cleared.
Bit 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*The number of channels is device dependent. Refer to
the device pinout description.
DATA REGISTER (ADCDRH)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[9:2] MSB of Converted Analog Value
DATA REGISTER (ADCDRL)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Converted Analog Value
70
EOC
SPEED ADON
0
CH3
CH2
CH1
CH0
Channel Pin*
CH3
CH2
CH1
CH0
AIN0
0
AIN1
0
1
AIN2
0
1
0
AIN3
0
1
AIN4
0
1
0
AIN5
0
1
0
1
AIN6
0
1
0
AIN7
0
1
AIN8
1
0
AIN9
1
0
1
AIN10
1
0
1
0
AIN11
1
0
1
AIN12
1
0
AIN13
1
0
1
AIN14
1
0
AIN15
1
70
D9
D8
D7
D6
D5
D4
D3
D2
70
0
000
00
D1
D0
1
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