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| 型號(hào)： | ST72324BLK4BA/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | 0.400 INCH, PLASTIC, SDIP-32 |
| 文件頁(yè)數(shù)： | 72/151頁(yè) |
| 文件大?。?/td> | 1209K |
| 代理商： | ST72324BLK4BA/XXX |
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ST72F324L, ST72324BL
27/151
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit-
ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc-
ess shown in Figure 14.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
7.4 CONCURRENT & NESTED MANAGEMENT
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 16. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0. The software priority is giv-
en for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
Figure 15. Concurrent Interrupt Management
Figure 16. Nested Interrupt Management
MAIN
IT4
IT2
IT1
TRAP
IT1
MAIN
IT0
I1
HARD
WARE
PRIORITY
SOFTWARE
3
3/0
3
11
11 / 10
11
RIM
IT2
IT1
IT4
TRAP
IT3
IT0
IT3
I0
10
PRIORITY
LEVEL
USED
STACK
=
10
BYTES
MAIN
IT2
TRAP
MAIN
IT0
IT2
IT1
IT4
TRAP
IT3
IT0
HARD
WARE
PRIORITY
3
2
1
3
3/0
3
11
00
01
11
RIM
IT1
IT4
IT1
IT2
IT3
I1
I0
11 / 10
10
SOFTWARE
PRIORITY
LEVEL
USED
STACK
=
20
BY
TES
1
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| ST72324BLK4TA | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE |
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