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| 型號(hào)： | ST72521R7T5/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, PLASTIC, TQFP-64 |
| 文件頁(yè)數(shù)： | 40/199頁(yè) |
| 文件大?。?/td> | 1979K |
| 代理商： | ST72521R7T5/XXX |
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ST72521M/R/AR
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CONTROLLER AREA NETWORK (Cont’d)
10.8.4 Register Description
The CAN registers are organized as 6 general pur-
pose registers plus 5 pages of 16 registers span-
ning the same address space and primarily used
for message and filter storage. The page actually
selected is defined by the content of the Page Se-
lection Register. Refer to Figure 72.
10.8.4.1 General Purpose Registers
INTERRUPT STATUS REGISTER (ISR)
Read/Write
Reset Value: 00h
Bit 7 = RXIF3
Receive Interrupt Flag for Buffer 3
Read/Clear
Set by hardware to signal that a new error-free mes-
sage is available in buffer 3.
Cleared by software to release buffer 3.
Also cleared by resetting bit RDY of BCSR3.
Bit 6 = RXIF2
Receive Interrupt Flag for Buffer 2
Read/Clear
Set by hardware to signal that a new error-free
message is available in buffer 2.
Cleared by software to release buffer 2.
Also cleared by resetting bit RDY of BCSR2.
Bit 5 = RXIF1
Receive Interrupt Flag for Buffer 1
Read/Clear
Set by hardware to signal that a new error-free mes-
sage is available in buffer 1.
Cleared by software to release buffer 1.
Also cleared by resetting bit RDY of BCSR1.
Bit 4 = TXIF
Transmit Interrupt Flag
Read/Clear
Set by hardware to signal that the highest priority
message queued for transmission has been suc-
cessfully transmitted (ETX = 0) or that it has passed
successfully the arbitration (ETX = 1).
Cleared by software.
Bit 3 = SCIF
Status Change Interrupt Flag
Read/Clear
Set by hardware to signal the reception of a domi-
nant bit while in standby or a change from error ac-
tive to error passive and bus-off while in run. Also
signals any receive error when ESCI = 1.
Cleared by software.
Bit 2 = ORIF
Overrun Interrupt Flag
Read/Clear
Set by hardware to signal that a message could not
be stored because no receive buffer was available.
Cleared by software.
Bit 1 = TEIF
Transmit Error Interrupt Flag
Read/Clear
Set by hardware to signal that an error occurred dur-
ing the transmission of the highest priority message
queued for transmission.
Cleared by software.
Bit 0 = EPND
Error Interrupt Pending
Read Only
Set by hardware when at least one of the three error
interrupt flags SCIF, ORIF or TEIF is set.
Reset by hardware when all error interrupt flags
have been cleared.
Caution;
Interrupt flags are reset by writing a "0" to the cor-
responding bit position. The appropriate way con-
sists in writing an immediate mask or the one’s com-
plement of the register content initially read by the
interrupt handler. Bit manipulation instruction
BRES should never be used due to its read-modify-
write nature.
70
RXIF3 RXIF2 RXIF1
TXIF
SCIF
ORIF
TEIF
EPND
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