參數(shù)資料
型號： ST7263BK1B/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝： 0.400 INCH, LEAD FREE, SHRINK, PLASTIC, DIP-32
文件頁數(shù)： 84/140頁
文件大小： 1423K
代理商： ST7263BK1B/XXX
ST7263B
48/140
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is fCPU/2, OCFi and
OCMPi are set while the counter value equals
the OCiR register value (see Figure 33 on page
49). This behaviour is the same in OPM or
PWM mode.
When the timer clock is fCPU/4, fCPU/8 or in
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure 34 on page 49).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
The FOLVLi bits have no effect in both one pulse
mode and PWM mode.
Figure 32. Output Compare Block Diagram
OUTPUT COMPARE
16-bit
CIRCUIT
OC1R Register
16 BIT
FREE RUNNING
COUNTER
OC1E
CC0
CC1
OC2E
OLVL1
OLVL2
OCIE
(Control Register 1) CR1
(Control Register 2) CR2
0
OCF2
OCF1
(Status Register) SR
16-bit
OCMP1
OCMP2
Latch
1
Latch
2
OC2R Register
Pin
FOLV2 FOLV1
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