參數(shù)資料
型號： ST72C171K2B6
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32
封裝： SHRINK, PLASTIC, DIP-32
文件頁數(shù)： 54/152頁
文件大?。?/td> 2156K
代理商： ST72C171K2B6
ST72C171
147/152
11 DEVICE CONFIGURATION AND
ORDERING INFORMATION
The device is available for production a user pro-
grammable version (FLASH). FLASH devices are
shipped to customers with a default content (FFh).
FLASH devices have to be configured by the cus-
tomer using the Option Bytes.
11.1 OPTION BYTES
The two option bytes allow the hardware configu-
ration of the microcontroller to be selected.
The option bytes have no address in the memory
map and can be accessed only in programming
mode (for example using a standard ST7 program-
ming tool). The default content of the FLASH is
fixed to FFh.
In masked ROM devices, the option bytes are
fixed in hardware by the ROM code (see option
list).
USER OPTION BYTE 0
Bit 7:1 = Reserved, must always be 1.
Bit 1= OA3E Op-Amp 3 Enable
This option bit enables or disables the third Op-
Amp of the on-chip Op-Amp Module.
0: OE3 disabled
1: OE3 enabled
Bit 0 = FMP Full memory protection.
This option bit enables or disables external access
to the internal program memory (read-out protec-
tion). Clearing this bit causes the erasing (to 00h)
of the whole memory (including the option byte).
0: Program memory not read-out protected
1: Program memory read-out protected
USER OPTION BYTE 1
Bit 7 = CFC Clock filter control on/off
This option bit enables or disables the clock filter
(CF) features.
0: Clock filter enabled
1: Clock filter disabled
Bit 6:4 = OSC[2:0] Oscillator selection
These three option bits can be used to select the
main oscillator as shown in Table 25.
Bit 3:2 = LVD[1:0] Low voltage detection selection
These option bits enable the LVD block with a se-
lected threshold as shown in Table 26.
Bit 1 = WDG HALT Watchdog and halt mode
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Bit 0 = WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Table 25. Main Oscillator Configuration
Table 26. LVD Threshold Configuration
Selected Oscillator
OSC2 OSC1 OSC0
External Clock (Stand-by)
11
1
~4 MHz Internal RC
11
0
1~14 MHz External RC
10
X
Low Power Resonator (LP)
01
1
Medium Power Resonator (MP)
01
0
Medium Speed Resonator (MS)
00
1
High Speed Resonator (HS)
00
0
Configuration
LVD1 LVD0
LVD Off
11
Highest Voltage Threshold (
4.50V)
10
Medium Voltage Threshold (
4.05V)
01
Lowest Voltage Threshold (
3.45V)
00
USER OPTION BYTE 0
70
USER OPTION BYTE 1
70
Reserved
OA3E FMP
CFC
OSC
2
OSC
1
OSC
0
LVD1 LVD0
WDG
HALT
WDG
SW
Default
Value
1
11111
1
011
10
111
1
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