參數(shù)資料
型號： ST72E734J6D0
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP42
封裝： CERAMIC, SDIP-42
文件頁數(shù)： 20/144頁
文件大小： 1280K
代理商： ST72E734J6D0
ST72774/ST727754/ST72734
116/144
4.9 PWM/BRM GENERATOR (DAC)
4.9.1 Introduction
This PWM/BRM peripheral includes two types of
PWM/BRM outputs, with differing step resolutions
based on the Pulse Width Modulator (PWM) and
Binary Rate Multiplier (BRM) Generator technique
are available. It allows the digital to analog
conversion
(DAC)
when
used
with
external
filtering.
4.9.2 Main Features
s
Fixed frequency: fCPU/64
s
Resolution: T
CPU
s
10-Bit PWM/BRM generator with a step of
V
DD/2
10 (5mV if V
DD=5V)
4.9.3 Functional Description
4.9.3.1 PWM/BRM
The 10 bits of the 10-bit PWM/BRM are distributed
as 6 PWM bits and 4 BRM bits. The generator
consists of a 12-bit counter (common for all
channels), a comparator and the PWM/BRM
generation logic.
PWM Generation
The counter increments continuously, clocked at
internal
CPU
clock.
Whenever
the
6
least
significant bits of the counter (defined as the PWM
counter) overflow, the output level for all active
channels is set.
The state of the PWM counter is continuously
compared to the PWM binary weight for each
channel, as defined in the relevant PWM register,
and when a match occurs the output level for that
channel is reset.
This Pulse Width modulated signal must be
filtered, using an external RC network placed as
close as possible to the associated pin. This
provides an analog voltage proportional to the
average charge passed to the external capacitor.
Thus for a higher mark/space ratio (High time
much greater than Low time) the average output
voltage is higher. The external components of the
RC network should be selected for the filtering
level required for control of the system variable.
Each output may individually have its polarity
inverted by software, and can also be used as a
logical output.
Figure 69. PWM Generation
COUNTER
63
COMPARE
VALUE
OVERFLOW
000
t
PWM OUTPUT
t
T
CPU x 64
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