參數(shù)資料
型號： ST72E734J6D0
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP42
封裝： CERAMIC, SDIP-42
文件頁數(shù)： 89/144頁
文件大小： 1280K
代理商： ST72E734J6D0
ST72774/ST727754/ST72734
49/144
16-BIT TIMER (Cont’d)
4.3.3.5 Forced Compare Mode
In this section
i may represent 1 or 2.
The following bits of the CR1 register are used:
When the FOLV
i bit is set, the OLVLi bit is copied
to the OCMP
i pin. The FOLVi bit is not cleared by
software, only by a chip reset. The OLV
i bit has to
be toggled in order to toggle the OCMP
i pin when
it is enabled (OC
iE bit=1).
The OCF
i bit is not set, and thus no interrupt
request is generated.
4.3.3.6 One Pulse Mode
One Pulse mode enables the generation of a pulse
when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure
To use one pulse mode, select the following in the
the CR1 register:
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit
.
And select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then dedi-
cated to the Output Compare 1 function.
– Set the OPM bit.
– Select the timer clock CC1-CC0 (see Table 15
Clock Control Bits).
Load
the
OC1R
register
with
the
value
corresponding to the length of the pulse (see the
formula in Section 4.3.3.7).
Then, on a valid event on the ICAP1 pin, the
counter is initialized to FFFCh and OLVL2 bit is
loaded on the OCMP1 pin. When the value of the
counter is equal to the value of the contents of the
OC1R register, the OLVL1 bit is output on the
OCMP1 pin, (See Figure 35).
Note: The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an Out-
put Compare interrupt.
The ICF1 bit is set when an active edge occurs and
can generate an interrupt if the ICIE bit is set.
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
Figure 35.
One Pulse Mode Timing
FOLV2 FOLV1 OLVL2
OLVL1
event occurs
Counter is
initialized
to FFFCh
OCMP1 = OLVL2
Counter
= OC1R
OCMP1 = OLVL1
When
on ICAP1
One pulse mode cycle
COUNTER
....
FFFC FFFD FFFE
2ED0
2ED1 2ED2
2ED3
FFFC FFFD
OLVL2
OLVL1
ICAP1
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
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