參數(shù)資料
型號(hào)： ST72P621J4T1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO34
封裝： PLASTIC, SO-34
文件頁數(shù)： 40/136頁
文件大小： 2475K
代理商： ST72P621J4T1
134/136
15 IMPORTANT NOTES
15.1 UNEXPECTED RESET FETCH
If an interrupt request occurs while a "POP CC" in-
struction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
Workaround
To solve this issue, a "POP CC" instruction must
always be preceded by a "SIM" instruction.
15.2 HALT MODE POWER CONSUMPTION
WITH ADC ON
If the A/D converter is being used when Halt mode
is entered, the power consumption in Halt Mode
may exceed the maximum specified in the datash-
eet.
Workaround
Switch off the ADC by software (ADON=0) before
executing a HALT instruction.
15.3 A/ D CONVERTER ACCURACY FOR FIRST
CONVERSION
When the ADC is enabled after being powered
down (for example when waking up from HALT,
ACTIVE-HALT or setting the ADON bit in the AD-
CCSR register), the first conversion (8-bit or 10-
bit) accuracy does not meet the accuracy specified
in the datasheet.
Workaround
In order to have the accuracy specified in the da-
tasheet, the first conversion after a ADC switch-on
has to be ignored.
15.4 SCI WRONG BREAK DURATION
Description
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a long-
er duration than expected:
- 20 bits instead of 10 bits if M=0
- 22 bits instead of 11 bits if M=1.
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than expect-
ed.
Occurrence
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit frequen-
cy
of
19200
baud
(fCPU=8MHz
and
SCI-
BRR=0xC9), the wrong break duration occurrence
is around 1%.
Workaround
If this wrong duration is not compliant with the
communication protocol in the application, soft-
ware can request that an Idle line be generated
before the break character. In this case, the break
duration is always correct assuming the applica-
tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa-
bling interrupts.
The exact sequence is:
- Disable interrupts
- Reset and Set TE (IDLE request)
- Set and Reset SBK (Break Request)
- Re-enable interrupts
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