REV. 5.1.0 3.9 TEST FIFO ( T-FIFO ) This port is available for prog" />
參數(shù)資料
型號(hào): ST78C36ACJ44-F
廠商: Exar Corporation
文件頁數(shù): 26/27頁
文件大?。?/td> 0K
描述: IC UART FIFO 16B 44PLCC
標(biāo)準(zhǔn)包裝: 27
特點(diǎn): *
FIFO's: 16 字節(jié)
規(guī)程: 打印機(jī)
電源電壓: 5V
帶并行端口:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
ST78C36/36A
8
ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO
REV. 5.1.0
3.9
TEST FIFO ( T-FIFO )
This port is available for programmed I/O and DMA access. Data written to this port is stored in the FIFO if
FIFO-F = 0 and will be lost if FIFO-F = 1. During a read cycle from this port a FIFO under-run will return last
data read and FIFO-E remains coherent.
3.10
CONFIGURATION REGISTER A ( Cnfg-A )
This read-only register is available in ECR mode 111 only.
Cnfg-A Bits 1-0:
Forced to logic zero, this field is don’t care for PWord = 1 byte.
Cnfg-A Bit-2:
When transmitting, there is 1 byte waiting to be transmitted that does not affect FIFO-F.
Cnfg-A Bit-3:
Reserved, logic zero.
Cnfg-A Bits 6-4:
Indicates PWord = 1 byte (8-bit implementation).
Cnfg-A Bit-7:
Indicates ECP interrupts are pulsed.
3.11
CONFIGURATION REGISTER B ( Cnfg-B )
This register is available in ECR mode 111 only, and returns bits 0-5 as logic zero for the ST78C36CJ44. The
ST78C36CQ64 will allow programmed selection of the Interrupt and DMA channels after a system RESET
state of 001011 (bits 0-5).
Cnfg-B Bits 2-0:
With bit 2 forced low, select an 8-bit DMA channel per the following table:
TABLE 1: DMA CHANNEL SELECTION: CNFG-B BITS[2:0]
WRITE TO FIFO
READ FROM FIFO
DMA CHANNEL
X00
000
3
X01
001
1
X10
010
2
X11
011
3 (Default)
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