參數(shù)資料
型號(hào)： ST92163R4
英文描述： 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS. 20K ROM. 2K RAM. I 2 C. SCI. & MFT
中文描述： 16位產(chǎn)品全速USB微控制器，16終點(diǎn)復(fù)合設(shè)備。 20,000光盤。 2K的RAM。余2長(zhǎng)脊髓損傷。
文件頁(yè)數(shù)： 195/230頁(yè)
文件大?。?/td> 2743K
代理商： ST92163R4
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195/230
ST92163 - I2C BUS INTERFACE
I
2
C BUS INTERFACE
(Cont’d)
INTERRUPT STATUS REGISTER (I2CISR)
R248 - Read / Write
Register Page: 20
Reset Value: 1xxx xxxx (xxh)
Bit 7 =
DMASTOP
DMA suspended mode
.
This bit selects between DMA suspended mode
and DMA not suspended mode.
In DMA Suspended mode, if the error interrupt
pending bit (I2CISR.IERRP) is set, no DMA re-
quest is performed. DMA requests are performed
only when IERRP=0. Moreover the “Error Condi-
tion” interrupt source has a higher priority than the
DMA.
In DMA Not-Suspended mode, the status of
IERRP bit has no effect on DMA requests. Moreo-
ver the DMA has higher priority with respect to oth-
er interrupt sources.
0: DMA Suspended mode
1: DMA Not-Suspended mode
Bits 6:4 =
PRL[2:0]
Interrupt/DMA Priority Bits
.
The priority is encoded with these three bits. The
value of “0” has the highest priority, the value “7”
has no priority. After the setting of this priority lev-
el, the priorities between the different Interrupt/
DMA sources is hardware defined according with
the following scheme:
– Error condition Interrupt (If DMASTOP=1) (High-
est priority)
– Receiver DMA request
– Transmitter DMA request
– Error Condition Interrupt (If DMASTOP=0
– Data Received/Receiver End Of Block
– Peripheral Ready To Transmit/Transmitter End
Of Block (Lowest priority)
Bit 3 = Reserved.
Must be cleared.
Bit 2 =
IERRP
Error Condition pending bit
0: No error
1: Error event detected (if ITE=1)
Note:
Depending
I2CISR.DMASTOP bit, this flag can suspend or
not suspend the DMA requests.
Note:
The Interrupt pending bits can be reset by
writing a “0” but is not possible to write a “1”. It is
mandatory to clear the interrupt source by writing a
“0” in the pending bit when executing the interrupt
service routine. When serving an interrupt routine,
the user should reset ONLY the pending bit related
to the served interrupt routine (and not reset the
other pending bits).
To detect the specific error condition that oc-
curred, the flag bits of the I2CSR1 and I2CSR2
register should be checked.
Note:
The IERRP pending bit is forced high while
the error event flags are set (ADSL and SB flags in
the I2CSR1 register, SCLF, ADDTX, AF, STOPF,
ARLO and BERR flags in the I2CSR2 register). If
at least one flag is set, it is not possible to reset the
IERRP bit.
on
the
status
of
the
Bit 1 =
IRXP
Data Received pending bit
0: No data received
1: data received (if ITE=1).
Bit 0 =
ITXP
Peripheral Ready To Transmit pend-
ing bit
0: Peripheral not ready to transmit
1: Peripheral ready to transmit a data byte (if
ITE=1).
7
0
DMASTOP PRL2 PRL1 PRL0
0
IERRP IRXP ITXP
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