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ST92141 - EXTENDED FUNCTION TIMER (EFT)
7.3 EXTENDED FUNCTION TIMER (EFT)
7.3.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (
input capture) or generation of up to two out-
put waveforms (
output compare and PWM).
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the INTCLK
prescaler.
7.3.2 Main Features
s
Programmable prescaler: INTCLK divided by 2,
4 or 8.
s
Overflow status flag and maskable interrupts
s
External clock input (must be at least 4 times
slower than the INTCLK clock speed) with the
choice of active edge
s
Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
s
Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
s
Pulse width modulation mode (PWM)
s
One pulse mode
s
5 alternate functions on I/O ports*
s
Up to 3 separate Timer interrupts or a global
interrupt (depending on device) mapped on
external interrupt channels:
– ICI: Timer Input capture interrupt.
– OCI: Timer Output compare interrupt.
– TOI: Timer Overflow interrupt.
– EFTI: Timer Global interrupt (replaces ICI,
OCI and TOI).
The Block Diagram is shown in Figure 53.
Table 21. EFT Pin Naming conventions
*Note 1: Some external pins are not available on
all devices. Refer to the device pin out description.
*Note 2: Refer to the device interrupt description,
to see if a single timer interrupt is used, or three
separate interrupts.
7.3.3 Functional Description
7.3.3.1 Counter
The principal block of the Programmable Timer is
a 16-bit free running counter and its associated
16-bit registers:
Counter Registers
– Counter High Register (CHR) is the most sig-
nificant byte (MSB).
– Counter Low Register (CLR) is the least sig-
nificant byte (LSB).
Alternate Counter Registers
– Alternate Counter High Register (ACHR) is the
most significant byte (MSB).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LSB).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (overflow
flag), (see note page 98).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 22 Clock
Control Bits. The value in the counter register re-
peats every 131.072, 262.144 or 524.288 INTCLK
cycles depending on the CC1 and CC0 bits.
Function
EFT0
EFT1
EFTn
Input Capture 1 -
ICAP1
ICAPA0
ICAPA1
ICAPAn
Input Capture 2 -
ICAP2
ICAPB0
ICAPB1
ICAPBn
Output Compare 1 -
OCMP1
OCMPA0 OCMPA1 OCMPAn
Output Compare 2 -
OCMP2
OCMPB0 OCMPB1 OCMPBn
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