
Samsung ASIC
4-99
STD130
PvSCKDCby
Input Clock Driver
Switching Characteristics
PSCKDCD2
(Typical process, 25
°
C, 1.8V, t
R
/t
F
= 1.50ns, SL: Standard Load)
PSCKDCD4
PSCKDCD6
PSCKDCD8
Path
Parameter
Delay [ns]
SL = 2
0.101
0.097
0.381
0.355
<
Delay Equations [ns]
Group1*
0.097 + 0.002*SL
0.094 + 0.002*SL
0.380 + 0.001*SL
0.353 + 0.001*SL
Group2*
0.079 + 0.002*SL
0.074 + 0.002*SL
0.381 + 0.001*SL
0.355 + 0.001*SL
Group3*
0.066 + 0.002*SL
0.062 + 0.002*SL
0.380 + 0.001*SL
0.354 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 275, *Group2 : 275 <
Path
Parameter
Delay [ns]
SL = 2
0.138
0.126
0.500
0.477
<
Delay Equations [ns]
Group1*
0.136 + 0.001*SL
0.124 + 0.001*SL
0.499 + 0.000*SL
0.476 + 0.000*SL
Group2*
0.116 + 0.001*SL
0.104 + 0.001*SL
0.507 + 0.000*SL
0.481 + 0.000*SL
Group3*
0.099 + 0.001*SL
0.085 + 0.001*SL
0.507 + 0.000*SL
0.480 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 549, *Group2 : 549 <
Path
Parameter
Delay [ns]
SL = 2
0.172
0.157
0.597
0.576
<
Delay Equations [ns]
Group1*
0.171 + 0.001*SL
0.156 + 0.001*SL
0.597 + 0.000*SL
0.576 + 0.000*SL
Group2*
0.150 + 0.001*SL
0.134 + 0.001*SL
0.612 + 0.000*SL
0.586 + 0.000*SL
Group3*
0.132 + 0.001*SL
0.114 + 0.001*SL
0.616 + 0.000*SL
0.587 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 823, *Group2 : 823 <
Path
Parameter
Delay [ns]
SL = 2
0.203
0.185
0.684
0.662
<
Delay Equations [ns]
Group1*
0.202 + 0.000*SL
0.185 + 0.000*SL
0.684 + 0.000*SL
0.662 + 0.000*SL
Group2*
0.183 + 0.000*SL
0.162 + 0.000*SL
0.704 + 0.000*SL
0.678 + 0.000*SL
Group3*
0.164 + 0.000*SL
0.143 + 0.000*SL
0.712 + 0.000*SL
0.681 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 1096, *Group2 : 1096 <