
Samsung ASIC
4-125
STD130
PHSOSCK17/K27/M16/M26/M36
3.3V Interface Oscillator Cell with Enable and Feedback Resistor
Switching Characteristics
PHSOSCK17
(Typical process, 25
°
C, 1.8V, 3.3V, t
R
/t
F
= 3.00ns, CL: Capacitive Load[pF])
Delay Equations [ns]
(Typical process, 25
°
C, 1.8V, 3.3V, t
R
/t
F
= 3.00ns, SL: Standard Load)
Delay Equations [ns]
Path
Parameter
Delay [ns]
CL = 50.0pF
1787.900
1386.500
845.810
680.770
1794.900
1364.700
842.320
677.680
<
Group1*
38.150 + 34.995*CL
37.175 + 26.986*CL
27.885 + 16.358*CL
14.445 + 13.326*CL
42.900 + 35.040*CL
30.725 + 26.680*CL
16.820 + 16.510*CL
12.855 + 13.296*CL
Group2*
39.500 + 34.968*CL
38.100 + 26.968*CL
27.630 + 16.364*CL
14.110 + 13.333*CL
45.300 + 34.992*CL
30.700 + 26.680*CL
16.960 + 16.507*CL
12.840 + 13.297*CL
Group3*
39.800 + 34.964*CL
38.100 + 26.968*CL
27.600 + 16.364*CL
14.200 + 13.332*CL
47.100 + 34.968*CL
30.700 + 26.680*CL
17.200 + 16.504*CL
12.900 + 13.296*CL
PADA to
PADY
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
E to PADY
*Group1 : CL < 50, *Group2 : 50 =
Path
Parameter
Delay [ns]
SL = 2
0.064
0.058
33.431
31.422
0.064
0.059
33.209
30.153
<
Group1*
0.060 + 0.002*SL
0.051 + 0.004*SL
33.427 + 0.002*SL
31.418 + 0.002*SL
0.060 + 0.002*SL
0.054 + 0.002*SL
33.206 + 0.001*SL
30.149 + 0.002*SL
Group2*
0.060 + 0.002*SL
0.055 + 0.003*SL
33.429 + 0.001*SL
31.418 + 0.002*SL
0.061 + 0.002*SL
0.052 + 0.003*SL
33.206 + 0.001*SL
30.150 + 0.002*SL
Group3*
0.061 + 0.002*SL
0.055 + 0.003*SL
33.432 + 0.001*SL
31.421 + 0.002*SL
0.060 + 0.002*SL
0.054 + 0.003*SL
33.210 + 0.001*SL
30.153 + 0.002*SL
PADA to
YN
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
E to YN
*Group1 : SL < 4, *Group2 : =