- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98147 > STEL-1173/CM (INTEL CORP) 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQCC44 PDF資料下載
參數(shù)資料
| 型號(hào)： | STEL-1173/CM |
| 廠商： | INTEL CORP |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 188K |
| 代理商： | STEL-1173/CM |
5
STEL-1173
CLOCK
All synchronous functions performed within the NCO
are referenced to the rising edge of the CLOCK input.
The CLOCK signal should be nominally a square
wave at a maximum frequency of 50 MHz. A non-
repetitive CLOCK waveform is permissible as long as
the minimum duration positive or negative pulse on
the waveform is always greater than 8 nanoseconds.
At each positive transition of the CLOCK signal, the
number stored in the
-Phase register is added to the
contents of the phase accumulator and the result is
placed in the phase accumulator.
WRN
On the rising edge of the WRN input, the information
on the 8-bit data bus is transferred to the buffer register
selected by the ADDR
2-0 bus.
CSN
The CSN (Chip Select) input is active low and can be
used to control the writing of data into the chip. When
this input is high all data writing via the DATA
7-0 bus
is inhibited.
ADDR
2
through ADDR
0
The three address lines ADDR
2-0 control the use of the
DATA
7-0 bus for writing frequency data to the -Phase
buffer registers as shown in the table below:
ADDR
2 ADDR1 ADDR0 -Phase Register Field
0
Bits0 (LSB) –7
0
1
Bits 8–15
0
1
0
Bits 16–23
0
1
Bits 24–31
1
0
Bits 32–39
1
0
1
Bits 40–47 (MSB)
To write to all 48 bits of the phase write registers, the
DATA
7-0 bus must be used 6 times. Note that it is not
necessary to reload unchanged bytes, and that the byte
loading sequence may be random.
DATA
7
through DATA
0
The eight bit DATA
7-0 bus is used to program the 48-
bit
-Phase register. DATA
0 is the least significant bit
of the bus.
LDSTB
On the rising edge of the clock following the falling
edge of the LDSTB input, the information in the 48-bit
buffer register is transferred to the
-Phase register.
The frequency of the NCO output will change 20 clock
cycles after the LDSTB command due to pipelining
delays.
CARRY IN
Normal operation of the NCO requires that CARRY
IN
be set at a logic 0. When CARRY IN is a logic 1, the
effective value of the
-Phase register is increased by
one. Two NCOs can be cascaded together to obtain 96
bits of frequency resolution by using the CARRY OUT
of the lower order NCO and the CARRY IN of the
higher order NCO.
TWOSCOMP
When the TWOSCOMP input is set high, the data
appearing on the OUT
11-0 bus is presented in two's
complement code, and when it is set low, the data is
presented in offset binary code. The limits of the data
values in both codes is shown below:
Code
→ Offset binary
2's Complement
Minimum value
+1 (001
H)
– 2047 (801
H)
Maximum value +4095 (FFF
H)
+2047 (7FF
H)
Mean value
+2048 (800
H)
0 (000
H)
Both number formats produce sine or cosine waves
which are symmetrical about the phase quadrant axis
and the mean-value magnitude axis.
SINE
When the SINE input signal is set to a logic low level,
the output signal appearing on the OUT
11-0 bus is the
cosine of the 48-bit accumulator’s 13 most significant
bits (bits 47-35, with 47 being the MSB). Normally set
high, this signal allows the NCO to generate either sine
or cosine signals. By using two devices, one set in the
sine mode and the other set in the cosine mode,
quadrature outputs may be obtained. The quadrature
phase relationship of the two outputs will be
maintained at all times provided the two devices are
reset simultaneously and operate from a common
clock signal.
A high level on the SINE input sets the output to be the
sine of the 48-bit accumulator’s 13 most significant
bits. The value of the output for a given phase value
follows the relationship:
2’s comp = 2047 x sin (360 x phase)
offset bin = 2047 x sin (360 x phase) +2048
The result is accurate to within 1 LSB.
When this input is set low the output will be the cosine
of the 48-bit accumulator’s 13 most significant bits.
The value of the output for a given phase value follows
the relationship:
2’s comp = 2047 x cos (360 x phase)
offset bin = 2047 x cos (360 x phase) +2048
again, accurate to within 1 LSB.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STEL-1375A+80 | SPECIALTY MICROPROCESSOR CIRCUIT, DIP35 |
| STEL-1376 | SPECIALTY MICROPROCESSOR CIRCUIT, DIP65 |
| STEL-1377Q | SPECIALTY MICROPROCESSOR CIRCUIT, DIP63 |
| STK1390-5S25I | 0 TIMER(S), REAL TIME CLOCK, PDSO32 |
| STK1390-5S30I | 0 TIMER(S), REAL TIME CLOCK, PDSO32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STEL-1173RH/MD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Numeric-Controlled Oscillator |
| STEL-1176/CM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Numeric-Controlled Oscillator |
| STEL-1176/MC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Numeric-Controlled Oscillator |
| STEL-1177/CC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Numeric-Controlled Oscillator |
| STEL-1177/CF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Numeric-Controlled Oscillator |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。