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參數(shù)資料
| 型號： | STEL-1173/CM |
| 廠商： | INTEL CORP |
| 元件分類： | 數(shù)字信號處理外設 |
| 英文描述： | 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 188K |
| 代理商： | STEL-1173/CM |
7
STEL-1173
D.C. CHARACTERISTICS (Operating Conditions: V
DD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 70° C, Commercial
Symbol
Parameter
Min.
Typ.
Max.
Units
Conditions
IDD(Q)
Supply Current, Quiescent
1.0
mA
Static, no clock
IDD
Supply Current, Operational
3.0 mA/MHz
VIH(min)
High Level Input Voltage
Standard Operating Conditions
2.0
volts
Logic '1'
Extended Operating Conditions
2.25
volts
Logic '1'
VIL(max)
Low Level Input Voltage
0.8
volts
Logic '0'
IIH(min)
High Level Input Current
10
35
110
A
CIN
and CSEL, VIN = VDD
IIH(min)
High Level Input Current
10
A
All other inputs, VIN = VDD
IIL(max)
Low Level Input Current
–10
A
CIN
and CSEL, VIN = VSS
IIL(max)
Low Level Input Current
–15
–45
–130
A
All other inputs, VIN = VSS
VOH(min)
High Level Output Voltage
2.4
4.5
volts
IO = –4.0 mA
VOL(max)
Low Level Output Voltage
0.2
0.4
volts
IO = +4.0 mA
IOS
Output Short Circuit Current
20
65
130
mA
VOUT = VDD, VDD = max
–10
–45
–130
mA
VOUT = VSS, VDD = max
CIN
Input Capacitance
2
pF
All inputs
COUT
Output Capacitance
4
pF
All outputs
A.C. CHARACTERISTICS (Operating Conditions: V
DD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 70° C, Commercial
STEL-1173
(Commercial)
Symbol
Parameter
Min.
Max
Units
Conditions
tRS
RESET
pulse width
30
nsec.
tSR
RESET
to CLOCK Setup
10
nsec.
tSU
DATA
, ADDR or CSEL
18
nsec.
to WRN Setup, and
LDSTB
to CLOCK Setup
tHD
DATA
, ADDR or CSEL
12
nsec.
to WRN Hold, and
LDSTB
to CLOCK Hold
tCH
CLOCK
high
8
nsec.
fCLK = max.
tCL
CLOCK
low
8
nsec.
fCLK = max.
tW
WRN
or FRLD pulse width
20
nsec.
tCD
CLOCK
to output delay
5
10
nsec.
Load = 15 pF
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