參數(shù)資料
型號(hào): STEL-1375A+80
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, DIP35
封裝: 2.500 X 1.300 INCH, 0.350 INCH HEIGHT, DIP-35
文件頁(yè)數(shù): 11/13頁(yè)
文件大?。?/td> 202K
代理商: STEL-1375A+80
7
STEL-1375A+80
D.C. CHARACTERISTICS (Operating Conditions: VDD = 5.0 V ±5%, VEE = -5.2 V ±5%, Ta = 25°C)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IDD
Supply Current, +5 volts
250
mA
@ 80 MHz clock
IEE
Supply Current, –5.2 volts
200
mA
@ 80 MHz clock
VIH(min)
Min. High Level Input Voltage
2.0
volts
Guaranteed Logic '1'
VIL(max)
Max. Low Level Input Voltage
0.8
volts
Guaranteed Logic '0'
IIH(max)
Max. High Level Input Current
10
35
110
AV
IN = +5.0 volts
IIL(max)
Max. Low Level Input Current
–10
–45
–130
AV
IN = 0 volts
VCLK
Clock Input
0
+10
dBm
into 50
OUTPUT CHARACTERISTICS
Symbol
Parameter
Min. Typ. Max. Units
Conditions
PO(max)
Max. Output Power
–5
–4
–2
dBm
50
load, f
OUT < .25 x fCLK
Err(i)
Output integral linearity
–0.1
+0.1
%
of full-scale output
VSPUR
Spurious signal level
–60
dBc
fOUT < .25 x fCLK
VSPUR
Spurious signal level
–55
dBc
fOUT > .25 x fCLK
A.C. CHARACTERISTICS (Operating Conditions: VDD = 5.0 V ±5%, VEE = -5.2 V ±5%, Ta = 25°C)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
tRS
Reset
30
nsec.
tSU
DATA
, ADDR or CSEL
5
nsec.
to WRSTB or PHLD Setup
tHD
DATA
, ADDR or CSEL
2
nsec.
to WRSTB or PHLD Hold
tCH
Clock high
7
nsec.
fCLK= 80 MHz
tCL
Clock low
7
nsec.
fCLK= 80 MHz
tWR
WRSTB
pulse width
7
nsec.
tLS
FRLD
or PHLD pulse width
7
nsec.
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