- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98147 > STEL-1375A+80 (INTEL CORP) SPECIALTY MICROPROCESSOR CIRCUIT, DIP35 PDF資料下載
參數(shù)資料
| 型號： | STEL-1375A+80 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, DIP35 |
| 封裝： | 2.500 X 1.300 INCH, 0.350 INCH HEIGHT, DIP-35 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 202K |
| 代理商： | STEL-1375A+80 |
5
STEL-1375A+80
is selected (ADDR3-0 =1000), DATA7-4 is written into
Bits 3–0 of the register. In all cases, it is not necessary
to reload unchanged bytes, and the byte loading
sequence can be random.
WRSTB
On the rising edge of the WRSTB input, the information
on the 8-bit data bus is transferred to the buffer register
selected by the ADDR3-0 bus.
FRSEL
When the Frequency Register Select line is high
-Phase Register 'A' is selected as the source for the
Phase Accumulator, and the frequency corresponding
to the data stored in this register will be generated by
the NCO after the next FRLD command. When this
line is low,
-Phase Register 'B' is selected as the
source.
FRLD
On the rising edge of the clock following the falling
edge of the Frequency Load input, the information in
the 32-bit Buffer Register is transferred to the
-Phase
Register. The frequency of the DDS output will change
20 clock cycles after the FRLD command due to
pipelining delays.
PHSEL
When the Phase Source Select line is set high the
source for the phase modulation data is the phase
modulation register. It is loaded from the DATA7-0
bus by setting address line ADDR3 high, as shown in
the tables. When this line is set low, the sources for the
phase modulation data are the DATA7-0 bus and the
ADDR3-0 bus, and data will be loaded directly from
these inputs independently of the states of WRSTB
and CSEL. The data on these 12 inputs is presented
directly as a parallel 12-bit word to the phase modulator,
allowing high-speed phase modulation. The data on
the ADDR3-0 lines are mapped onto Phase Bits 3 to 0
and the data on the DATA7-0 lines are mapped onto
Phase Bits 11 to 4 in this case. When using the parallel
phase load mode CSEL and/or WRSTB should remain
high to ensure that the phase data is not written into the
phase and frequency buffer registers of the STEL-
1375A+80.
PHLD
The 12-bit data at the input of the phase modulator is
added to the output of the phase accumulator on the
rising edge of the clock following the falling edge of the
Ph
ase Load input. The source of this data will be
determined by the state of the PHSEL line. The phase
of the DDS output will change 13 clock cycles after the
PHLD
command, due to pipelining delays.
CIN
Normal operation of the NCO requires that Carry In be
set at a logic 0. When CIN is a logic 1, the effective
value of the
-Phase register is increased by one. Two
NCOs can be cascaded together to obtain 64 bits of
frequency resolution by using the COUT of the lower
order NCO and the CIN of the higher order NCO.
Only one DAC is used in this configuration, it is
connected to the higher significance NCO. If this
facility is used, the STEL-1375A+80 should be used for
the 32 MSBs of the 64-bit frequency control word, and
an STEL-1175 should be used for the 32 LSBs.
SINE
When the SINE input signal is set low the output
signal appearing on the OUT pin will be a cosine
function and when it is set high the DDS output will be
a sine function. After a reset the device will always
start at a phase angle of zero, irrespective of the status
of the SINE input. In this way, by using two devices,
one set in the sine mode and the other set in the cosine
mode, quadrature outputs may be obtained. The
quadrature phase relationship of the two outputs will
be maintained at all times provided the two devices are
operated from common RESET, FRLD and CLOCK
signals. The use of phase modulation will, of course,
modify this relationship, unless the devices are also
phase modulated together.
OUTPUT SIGNALS
OUT
The signal appearing on the OUT pin is the analog
output of the DAC. It is a stepped sinewave, where the
number of steps in each cycle of the output is equal to
the ratio of the clock frequency to the output frequency.
When this number is not an integer the steps will not
repeat from one cycle to the next, but the fundamental
component of the output signal will always be a
sinewave at the desired frequency. There will be a DC
offset on the output signal.
The output can be
capacitively coupled if operation down to very low
frequencies is not required, otherwise offset
compensation should be provided externally.
POWER SUPPLY
CONNECTIONS
It is recommended that adequate decoupling of the +5
volt and –5.2 volt power supplies be provided. In
addition, it is recommended that decoupling inductors
be used on the DVEE (DAC) and AVEE (DAC) supplies
to minimize the noise on the power supplies to the
DAC. Suitable values for the inductors are 0.3 to 1
H.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STEL-1376 | SPECIALTY MICROPROCESSOR CIRCUIT, DIP65 |
| STEL-1377Q | SPECIALTY MICROPROCESSOR CIRCUIT, DIP63 |
| STK1390-5S25I | 0 TIMER(S), REAL TIME CLOCK, PDSO32 |
| STK1390-5S30I | 0 TIMER(S), REAL TIME CLOCK, PDSO32 |
| STK1390-5S35 | 0 TIMER(S), REAL TIME CLOCK, PDSO32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STEL-1377Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FREQUENCY SYNTHESIZER|DIP|64PIN|PLASTIC |
| STEL-1377S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FREQUENCY SYNTHESIZER|DIP|64PIN|PLASTIC |
| STEL-1378A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FREQUENCY SYNTHESIZER|HYBRID|DIP|64PIN|PLASTIC |
| STEL-2000A+20/CR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RF MODULATOR/DEMODULATOR|CMOS|QFP|100PIN|PLASTIC |
| STEL-2000A+45/CR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RF MODULATOR/DEMODULATOR|CMOS|QFP|100PIN|PLASTIC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。