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參數(shù)資料
| 型號： | STEL-1376 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, DIP65 |
| 封裝： | 3.350 X 1.500 INCH, 0.350 INCH HEIGHT, DIP-65 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大小： | 233K |
| 代理商： | STEL-1376 |
7
STEL-1376
D.C. CHARACTERISTICS (Operating Conditions: VDD = 5.0 V ±5%, VEE = -5.2 V ±5%, Ta = 25°C)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IDD
Supply Current, +5 volts
380
mA
@ 80 MHz clock
IEE
Supply Current, –5.2 volts
460
mA
@ 80 MHz clock
VIH(min)
Min. High Level Input Voltage
2.0
volts
Guaranteed Logic '1'
VIL(max)
Max. Low Level Input Voltage
0.8
volts
Guaranteed Logic '0'
IIH(max)
Max. High Level Input Current
10
35
110
AV
IN = +5.0 volts
IIL(max)
Max. Low Level Input Current
–10
–45
–130
AV
IN = 0 volts
VCLK
Clock Input
0.4
1.0
volts
peak to peak
OUTPUT CHARACTERISTICS
Symbol
Parameter
Min. Typ. Max. Units
Conditions
PO(max)
Max. Output Power
–5
dBm
50
load, f
OUT < .25 x fCLK
Err(i)
Output integral linearity
–0.1
+0.1
%
of full-scale output
VSPUR
Spurious signal level
–65
dBc
fOUT < .25 x fCLK
VSPUR
Spurious signal level
–60
dBc
fOUT > .25 x fCLK
A.C. CHARACTERISTICS (Operating Conditions: VDD = 5.0 V ±5%, VEE = -5.2 V ±5%, Ta = 25°C)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
tRS
Reset pulse width
30
nsec.
tSU
Data, Address or CSN
5
nsec.
to WRN or PHLDSetup
tHD
Data, Address or CSN
2
nsec.
to WRN or PHLD Hold
tWR
WRN pulse width
7
nsec.
tLS
LDSTB or PHLD pulse width
7
nsec.
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