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參數(shù)資料
| 型號： | STEL-1376 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, DIP65 |
| 封裝： | 3.350 X 1.500 INCH, 0.350 INCH HEIGHT, DIP-65 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 233K |
| 代理商： | STEL-1376 |
5
STEL-1376
ADDR2 through ADDR0
The three address lines ADDR2-0 control the use of the
DATA34-0 bus for writing frequency data to the -
Phase Buffer Register and the PHASE2-0 bus for
writing phase data to the Phase Buffer Register, as
shown in the table:
ADDR2 ADDR1 ADDR0 Register Field
00
0
-Phase Bits 7-0 (LSB)1
00
1
-Phase Bits 15-81
01
0
-Phase Bits 23-161
01
1
-Phase Bits 30-241
10
0
-Phase Bits 34-321
1
0
1
Phase Bits 2-0
11
0
-Phase Bits 34-02
11
1
-Phase + Phase Bits3
It is not necessary to reload unchanged bytes, and the
byte loading sequence may be random.
Notes: 1. Byte-wide frequency loading mode.
2. Parallel frequency loading mode.
3. Loads the frequency data in the
parallel mode and the phase data
simultaneously.
WRSTB
The Write Strobe input is used to latch the data on the
DATA34-0 and PHASE2-0 busses into the device. On the
rising edge of the WRSTB input, the information on
the busses is transferred to the buffer register selected
by the ADDR2-0 bus.
FRLD
The Frequency Load input is used to control the
transfer of the data from the
-Phase Buffer Registers
to the
-Phase Register. The data at the output of the
Buffer Registers must be valid from the falling edge of
FRLD
until after the next rising edge of LDCLK. The
data is then transferred during the subsequent cycle.
The frequency of the NCO output will change 37 clock
cycles after the FRLD command due to pipelining
delays if LDCLK was low at the time; otherwise it will
change 38 clock cycles later.
PHLD
The Phase Load input is used to control the transfer of
the data from the Phase Buffer Registers to the Phase
ALU. The data at the output of the Buffer Register
must be valid from the falling edge of PHLD until after
the next rising edge of LDCLK. The data is then
transferred during the subsequent cycle. The phase of
the NCO output will change 17 clock cycles after the
PHLD
command due to pipelining delays if LDCLK
was low at the time; otherwise it will change 18 clock
cycles later.
CIN
The Carry Input is an arithmetic carry to the least
significant bit of the Accumulator. Normal operation
of the NCO requires that CIN be set at a logic 0. When
CIN
is set at a logic 1 the effective value of the
-Phase
register is increased by one. This allows the resolution
of the accumulator to be expanded for higher
frequency resolution.
CLKSEL
The Clock Select input selects the frequency of the
REFCLK
output. When CLKSEL is set low the
frequency of REFCLK will be the CLOCK frequency
divided by eight, and when it is set high the frequency
will be the CLOCK frequency divided by sixteen.
VREF
The VREF input is the input to the reference buffer of
the DAC. It is connected as shown in the diagram in the
Applications Information section. The output level of
the STEL-1376 can be varied by adjusting the
potentiometer. The full-scale output voltage is
proportional to (VSS–VREF), and consequently it is
recommended that a zener diode be used to stabilize
this voltage as shown, rather than a resistive divider,
unless the stability of the output level is not critical.
The output can be amplitude modulated by means of
this input. In the circuit shown the modulation could
be capacitively coupled directly to VREF. For more
information on the use of the VREF input please refer
to the Sony CX20201A-1 data sheet.
OUTPUT SIGNALS
OUT
The signal appearing on the OUT pin is the analog
output of the DAC. It is a stepped sinewave, where the
number of steps in each cycle of the output is equal to
the ratio of the clock frequency to the output
frequency. When this number is not an integer the
steps will not repeat from one cycle to the next, but the
fundamental component of the output signal will
always be a sinewave at the desired frequency. There
will be a DC offset on the output signal. The output can
be capacitively coupled if operation down to very low
frequencies is not required, otherwise offset
compensation should be provided externally.
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