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參數(shù)資料
| 型號： | STEL-1377Q |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, DIP63 |
| 封裝： | 3.750 X 1.600 INCH, 0.40 INCH HEIGHT, DIP-63 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 231K |
| 代理商： | STEL-1377Q |
STEL-1377Q/S
6
SIMLD
The Simultaneous Load input allows the carrier
frequency data from the Mux Block and the FM data to
be updated simultaneously. When SIMLD is low,
only the FM data will be updated after a falling edge on
FMLD
. When this input is high, both the FM data and
carrier
frequency
data
will
be
updated
simultaneously. When SIMLD is low at least four
clock cycles are required between falling edges of
FMLD
and FRLD to ensure glitch-free changes in the
outputs.
RATE1-0
The RATE1-0 signals control the rate at which the FM
data on the FMOD15-0 bus is added to or subtracted
from the carrier frequency, as shown in the table
below:
RATE1 RATE0
Modulation Update Rate
0
Manual, with FMLD signal
0
1
Every 4th clock cycle
1
0
Every 8th clock cycle
1
Every 16th clock cycle
CIN
The Carry Input is an arithmetic carry to the least
significant bit of the Accumulator. Normal operation
of the NCO requires that CIN be set at a logic 0. When
CIN
is set at a logic 1 the effective value of the
-Phase
register is increased by one. This allows the resolution
of the accumulator to be expanded for higher
frequency resolution.
OUTPUT SIGNALS
OUT (SIN) AND OUT (COS)
The signals appearing on the OUT pins are the analog
outputs of the DACs. They are stepped sinewaves,
where the number of steps in each cycle of the output
is equal to the ratio of the clock frequency to the output
frequency. When this number is not an integer the
steps will not repeat from one cycle to the next, but the
fundamental component of the output signal will
always be a sinewave at the desired frequency. There
will be a DC offset on the output signal. The outputs
can be capacitively coupled if operation down to very
low frequencies is not required, otherwise offset
compensation should be provided externally.
FMSYNC
The FM Sync output indicates the instant in time when
the FM data on the FMOD bus is written into the
device. The FMSYNC output is normally high and
goes low for one clock cycle at a frequency depending
on the state of the RATE1-0 inputs. In the automatic
modulation modes (RATE1-0 ≠ 00) the data on the
FMOD15-0 bus will be written into the FM Buffer
Register on the rising edge of the clock following the
falling edge of FMSYNC. This signal can be used to
synchronize the updating of the FM data externally.
APPLICATIONS INFORMATION
Since the STEL-1377 combines high-speed digital and
analog circuits, care must be taken to minimize the
effects of noise from the digital circuit on the analog
output. The following precautions will help in this
area:
1.
Use ground and power planes on the printed
circuit board. Separate analog and digital ground
planes will also help.
2.
Decouple the DVEE (DAC) and AVEE (DAC) line
from the VEE supply with 0.3 to 1 H inductors.
3.
Decouple all the power supply pins and the VREF
pin to the appropriate ground plane with 1000 pF
and 0.1
F ceramic capacitors mounted as closely
as possible to the pins.
The clock input can be either a sine wave or a square
wave, the input buffer will square up a sinusoidal
input. The input is capacitively coupled internally. An
ECL level signal or a sine wave at about –5 to +5 dBm
(50
) is recommended. The bias circuit shown can be
used to generate a stable VREF. If high stability, which
translates directly into output level stability, is not a
requirement a much simpler circuit can be realized by
replacing the 2.7K
and 2.2K resistors and the
reference diode with a single 8.2K
resistor from
VREF to the analog ground. The output level can be
varied by adjusting the bias voltage with the 2K
pot
in either case.
62
59
58
STEL-1377
Ana. GND
2 K
VREF
V SS
AV EE
2, 61, 57
V EE , DV EE
–5.2 V
(Ana.)
2.7 K
2.2 K
2.5 V
–5.2 V (Dig.)
Dig.
GND
V SS
46, 54
V DD
52, 56
+5 V
Recommended bias circuit for VREF
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