參數(shù)資料
型號(hào): STEL-1377Q
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, DIP63
封裝: 3.750 X 1.600 INCH, 0.40 INCH HEIGHT, DIP-63
文件頁(yè)數(shù): 12/13頁(yè)
文件大?。?/td> 231K
代理商: STEL-1377Q
STEL-1377Q/S
8
DDS FREQUENCY CHANGE SEQUENCE
A.C. CHARACTERISTICS (Operating Conditions: VDD=5.0 V ±5%, VEE=–5.2 V ±5%, Ta=25°C)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
tRS
Reset Pulse Width
20
nsec.
tSU
DATA
, ADDR or CSEL
5
nsec.
to WRSTB or PHLD Setup
and FRLD, PHLD, FMLD
or FMOD to CLOCK Setup
tHD
DATA
, ADDR or CSEL
5
nsec.
to WRSTB or PHLD Setup
and FRLD, PHLD, FMLD
or FMOD to CLOCK Hold
tCH
CLOCK
high
5
nsec.
fCLK= 60 MHz
tCL
CLOCK
low
5
nsec.
fCLK= 60 MHz
tW
WRSTB
, FRLD, PHLD
or FMLD pulse width
5
nsec.
NEW FREQUENCY
OLD FREQUENCY
1
2
3
20 CLOCK
EDGES
DON'T CARE
OUT
FRLD
FSYNC
CLOCK
WRSTB
CSEL
ADDR 3-0
DON'T CARE
DATA 7-0
tSU
19
20
tHD
tW
tSU
tW
tCL
tCH
DON'T CARE
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