參數(shù)資料
型號： STK11C68-5C55M
廠商： Electronic Theatre Controls, Inc.
英文描述： CMOS NV SRAM
中文描述： 的CMOS非易失SRAM
文件頁數(shù)： 8/10頁
文件大?。?/td> 59K
代理商： STK11C68-5C55M
STK11C68-M
4-38
The STK11C68-M has two separate modes of opera-
tion: SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as an ordinary static
RAM. In nonvolatile operation, data is transferred from
SRAM to EEPROM or from EEPROM to SRAM. In this
mode SRAM functions are disabled.
SRAM READ
The STK11C68-M performs a READ cycle whenever
E and G are LOW while W is HIGH. The address
specified on pins A
0-12
determines which of the 8192
data bytes will be accessed. When the READ is
initiated by an address transition, the outputs will be
valid after a delay of t
AVQV
(READ CYCLE #1). If the
READ is initiated by E or G, the outputs will be valid at
t
ELQV
or at t
GLQV
, whichever is later (READ CYCLE #2).
The data outputs will repeatedly respond to address
changes within the t
AVQV
access time without the need
for transitions on any control input pins, and will remain
valid until another address change or until E or G is
brought HIGH or W is brought LOW.
The STK11C68-M is a high speed memory and there-
fore must have a high frequency bypass capacitor of
approximately 0.1
μ
F connected between DUT V
CC
and V
SS
using leads and traces that are as short as
possible. As with all high speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
SRAM WRITE
A write cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W go HIGH at the end of the cycle. The
data on pins DQ
0-7
will be written into the memory if it
is valid t
DVWH
before the end of a W controlled WRITE
or t
DVEH
before the end of an E controlled WRITE.
It is recommended that G be kept HIGH during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers t
WLQZ
after W goes LOW.
NONVOLATILE STORE
The STK11C68-M STORE cycle is initiated by execut-
ing sequential READ cycles from six specific address
locations. By relying on READ cycles only, the
STK11C68-M implements nonvolatile operation while
remaining pin-for-pin compatible with standard 8Kx8
SRAMs. During the STORE cycle, an erase of the
previous nonvolatile data is first performed, followed
by a program of the nonvolatile elements. The pro-
gram operation copies the SRAM data into nonvolatile
elements. Once a STOREcycle is initiated, further
input and output are disabled until the cycle is com-
pleted.
Because a sequence of reads from specific addresses
is used for STORE initiation, it is important that no
other read or write accesses intervene in the sequence
or the sequence will be aborted and no STORE or
RECALL will take place.
To initiate the STORE cycle the following READ se-
quence must be performed:
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0F (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORECycle
Once the sixth address in the sequence has been
entered, the STOREcycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles be used in the sequence, although
it is not necessary that G be LOW for the sequence to
be valid. After the t
STORE
cycle time has been fulfilled,
the SRAM will again be activated for READ and WRITE
operation.
HARDWARE PROTECT
The STK11C68-M offers hardware protection against
inadvertent STORE cycles through V
CC
Sense. A
STOREcycle will not be initiated, and one in progress
will discontinue, if V
CC
goes below 4.0V. 4.0V is a
typical, characterized value. The datasheet specifica-
tions are guaranteed only for V
CC
= 5.0
+
10%.
NONVOLATILE RECALL
A RECALLcycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALLcycle the following sequence of READ op-
erations must be performed:
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0E (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALLCycle
DEVICE OPERATION
相關PDF資料
PDF描述
STK11C68-5K35M CMOS NV SRAM
STK11C68-5K45M CMOS NV SRAM
STK11C68-5K55M CMOS NV SRAM
STK11C68-5L35M CMOS NV SRAM
STK11C68-5L45M CMOS NV SRAM
相關代理商/技術參數(shù)
參數(shù)描述
STK11C68-5K35M 功能描述:NVRAM 8Kbx8 4.5-5.5V Softstore RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube
STK11C68-5K45M 功能描述:NVRAM 8Kbx8 4.5-5.5V Softstore RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube
STK11C68-5K55M 功能描述:NVRAM 8Kbx8 4.5-5.5V Softstore RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube
STK11C68-5L30M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based)
STK11C68-5L35M 功能描述:NVRAM 8Kbx8 4.5-5.5V Softstore RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube
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