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參數(shù)資料
| 型號： | STP2011PGA50 |
| 元件分類： | 參考電壓二極管 |
| 英文描述： | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| 中文描述： | 250 的低電流運(yùn)算，低反向泄露，低噪聲穩(wěn)壓二極管 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大小： | 221K |
| 代理商： | STP2011PGA50 |
DATA SHEET
1
STP2000QFP
Master I/O
32-bit SBus Master I/ O Controller
D
ESCRIPTION
The STP2000 Master I/ O Controller is an integrated SBus master device with built-in standard I/ O capabili-
ties for general purpose computing or embedded applications. The STP2000 directly interfaces the CPU
through the system bus, SBus, to three major I/ O channels for peripherals. The I/ O channels include SCSI-II,
ethernet and a parallel port. Together, with the STP2001 Slave I/ O Controller, it provides a complete I/ O
subsystem.
The STP2000 SBus interface is a 32-bit interface that supports both DMA and slave modes. There is data buff-
ering and flow control on each of the I/ O channels. Each channel has access to the SBus through the controller
which is capable of DMA transfers of up to 32-byte bursts. The SBus slave port is used mostly for status and
control.
The STP2000 incorporates an ethernet controller, a Fast 8-bit SCSI-II controller, and a Centronics parallel port
controller in a single package. The SCSI-II channel directly drives external peripherals. The ethernet channel
can be connected to an external transceiver chip that supports twisted pair ethernet or AUI ethernet. The par-
allel port channel can be routed to external transceivers.
Features
Benefits
Single-chip solution to standard SPARC DVMA devices
Compatible with microSPARC, SuperSPARC and any
SBus based system
Supports concurrent 10 MByte/sec SCSI transfers,
1.25 MByte/sec Ethernet transfers, and 4 MByte/sec
Parallel Port transfers
Direct master/slave SBus interface
JTAG internal and boundary SCAN logic
160-pin PQFP packaging
IC is also available from NCR Corp. (PN - NCR89C100)
Saves cost, power, board space, and weight
Standard low-cost solution
Improved system performance
Improved system performance
Improved chip and board level testability
Cost effective packaging
Second source
July 1997
This Material Copyrighted by Its Respective Manufacturer
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STP2012PQFP | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| STP2013PGA-50 | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| STP2014PQFP | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| STP2016QFP | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| STP2018TAB | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STP2012PQFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DMA Controller |
| STP2013PGA-50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
| STP2014PQFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
| STP2016QFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| STP2018TAB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
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