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參數(shù)資料
| 型號： | STP2011PGA50 |
| 元件分類： | 參考電壓二極管 |
| 英文描述： | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| 中文描述： | 250 的低電流運算，低反向泄露，低噪聲穩(wěn)壓二極管 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 221K |
| 代理商： | STP2011PGA50 |
10
STP2000QFP
32-bit SBus Master I/O Controller
Master I/O
July 1997
1. This is the only violation of SBus Specification B.0. No known implementation to date provides less than 1.0 ns hold time on these
signals.
AC Characteristics: SBus Timing
Signal #
Parameter
Conditions
Min
Max
Units
1
Clock Period
40.0
60.0
ns
2
Clock High
17.0
–
ns
3
Clock Low
17.0
–
ns
4
Hold wrt CLK Rising
0.0
–
ns
5
Setup to CLK Rising
Hold wrt CLK Rising
[1]
15.0
–
ns
6
1.0
–
ns
7
Hold wrt CLK Rising
0.0
–
ns
8
CLK Rising to Output Valid
160 pF load
2.5
22.5
ns
9
CLK Rising to Output Invalid
160 pF load
2.5
20.0
ns
AC Characteristics: Parallel Port Timing
Signal #
Parameter
Conditions
Min
Max
Units
10
CLK to P_D_STRB
75 pF
–
35
ns
11
P_D_STRB nominal width
DSW=0,1,2,3
3
–
SB_CLK periods
12
P_DATA valid to P_D_STRB assert
75 pF
5
–
ns
13
P_DATA valid (nominal)
DSS=0, DSN=3
6
–
SB_CLK periods
14
P_ACK, P_BSY setup to CLK
5
–
ns
15
P_ACK, P_BSY input pulse width
3
–
SB_CLK periods
16
P_D_STRB setup to CLK
5
–
ns
17
P_D_STRB input pulse width
3
–
SB_CLK periods
18
P_DATA setup to P_D_STRB
36
–
ns
19
P_DATA input hold from P_D_STRB
4
–
SB_CLK periods
20
P_D_STRB to P_BSY valid
75 pF
2
3 + 26 ns
SB_CLK periods
21
CLK to P_ACK, P_BSY
75 pF
–
40
ns
22
P_ACK, P_BSY nominal pulse width
75 pF
3
–
SB_CLK periods
23
CLK to output
75 pF
–
35
ns
This Material Copyrighted by Its Respective Manufacturer
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| STP2012PQFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DMA Controller |
| STP2013PGA-50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
| STP2014PQFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
| STP2016QFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| STP2018TAB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
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