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參數(shù)資料
| 型號： | STPC0375BTC3 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | PC Compatible Embeded Microprocessor |
| 中文描述： | PC兼容嵌入式微處理器 |
| 文件頁數(shù)： | 20/51頁 |
| 文件大?。?/td> | 726K |
| 代理商： | STPC0375BTC3 |
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PIN DESCRIPTION
20/51
Issue 1.2
ed to ISAOE# and the output is provided with a
weak pull-up resistor.
RTCRW# / DD[13]
Real Time Clock RW. This pin
is a multi-function pin. When ISAOE# is active,
this signal is used as RTCRW#. This signal is as-
serted for any I/O write to port 71H.
When ISAOE# is inactive, this signal is used as
IDE DD[13] signal.
This signal must be ORed externally with ISAOE#
and then connected to the RTC. An LS244 or
equivalent function can be used if OE is connect-
ed to ISAOE# and the output is provided with a
weak pull-up resistor.
RTCDS# /DD[12]
Real Time Clock DS This pin is
a multi-function pin. When ISAOE# is active, this
signal is used as RTCDS. This signal is asserted
for any I/O read to port 71H.
When ISAOE# is inactive, this signal is used as
IDE DD[12] signal.
This signal must be ORed externally with ISAOE#
and is then connected to RTC. An LS244 or equiv-
alent function can be used if OE# is connected to
ISAOE# and the output is provided with a weak
pull-up resistor.
RTCAS#
Real timeclock addressstrobe.This sig-
nal is asserted for any I/O write to port 70H.
2.2.12 Monitor Interface
RED, GREEN, BLUE
RGB Video Outputs. These
are the 3 analog color outputs from the RAMDACs
VSYNC
Vertical Synchronisation Pulse. This is
the vertical synchronization signal from the VGA
controller.
HSYNC
Horizontal Synchronisation Pulse. This is
the horizontal synchronization signal from the
VGA controller.
VREF_DAC
DAC Voltage reference. An external
voltage reference is connected to this pin to bias
the DAC.
RSET
Resistor Current Set.This is reference cur-
rent input to the RAMDAC is used to set the full-
scale output of the RAMDAC.
COMP
Compensation. This is the RAMDAC com-
pensation pin. Normally, an external capacitor
(typically 10nF) is connected between this pin and
V
DD
to damp oscillations.
DDC[1:0]
Direct Data Channel Serial Link. These
bidirectional pins are connected to CRTC register
3Fh to implement DDC capabilities. They conform
to I
2
C electrical specifications, they have open-
collector output drivers which are internally con-
nected to V
DD
through pull-up resistors.
They can instead be used for accessing I C devic-
es on board. DDC1 and DDC0 correspond toSCL
and SDA respectively.
COL_CMP
Color Compare Output Allows access
to the video signal which flags when there is a
color compare hit. This signal is multiplexed with
SMEMEW# onthe ISA Bus. The signal is selected
by setting Strap Option MD[0] as described in Sec-
tion3.
2.2.13 MISCELLANEOUS
SCAN_ENABLE
Reserved. The pins are re-
served for Test and Miscellaneous functions)
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