參數(shù)資料
型號(hào)： STPCCONSUMER-S
廠商： 意法半導(dǎo)體
英文描述： CONNECTOR ACCESSORY
中文描述： 連接器附件
文件頁(yè)數(shù)： 1/51頁(yè)
文件大?。?/td> 836K
代理商： STPCCONSUMER-S
STPC CONSUMER-S
PC Compatible Embeded Microprocessor
ADVANCED DATA
1/51
29/10/99
Release B
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figure 1. Logic Diagram
I
POWERFUL x86 PROCESSOR
64-BIT 66MHz SDRAM UMA CONTROLLER
VGA & SVGA CRT CONTROLLER
2D GRAPHICS ENGINE
VIDEO INPUT PORT
VIDEO PIPELINE
- UP-SCALER
- VIDEO COLOR SPACE CONVERTER
- CHROMA & COLOUR KEY SUPPORT
TV OUTPUT
- 3-LINE FLICKER FILTER
- CCIR 601/656 SCAN CONVERTER
- NTSC / PAL COMPOSITE, RGB, S-VIDEO
PCI MASTER / SLAVE CONTROLLER
ISA MASTER / SLAVE CONTROLLER
INTEGRATED PERIPHERAL CONTROLLER
- DMA CONTROLLER
- INTERRUPT CONTROLLER
- TIMER / COUNTERS
OPTIONAL 16-BIT LOCAL BUS INTERFACE
EIDE CONTROLLER
I C INTERFACE
POWER MANAGEMENT UNIT
3.3V OPERATION
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STPC CONSUMER-S OVERVIEW
The STPC Consumer-S integrates a standard 5th
generation x86 core, a Synchronous DRAM con-
troller, a graphics subsystem, a video input port,
video pipeline, and support logic including PCI,
ISA, and IDE controllers to provide a single con-
sumer orientated PC compatible subsystem on a
single device.
The device is based on a tightly coupled Unified
Memory Architecture (UMA), sharing the same
memory array between the CPU main memory
and the graphics and video frame buffers.
The STPC Consumer-S is packaged in a 388
Plastic Ball Grid Array (PBGA).
PBGA388
x86
Core
Host
I/F
SDRAM
CTRL
SVGA
CRTC
GE
VIP
PCI
m/s
LB
CTR
PCI Bus
ISA
m/s
IPC
PCI
m/s
ISA Bus
Cursor
Monitor
TV
IDE
I/F
PMU
W.dog
Video
Pipeline
C Key
K Key
LUT
Local Bus
Encoder
TVO
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