- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98149 > STPCC0166BTI3 (STMICROELECTRONICS) MULTIFUNCTION PERIPHERAL, PBGA388 PDF資料下載
參數(shù)資料
| 型號： | STPCC0166BTI3 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA388 |
| 封裝： | PLASTIC, BGA-388 |
| 文件頁數(shù)： | 5/71頁 |
| 文件大?。?/td> | 1238K |
| 代理商： | STPCC0166BTI3 |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁
Obsolete
Product(s)
- Obsolete
Product(s)
PIN DESCRIPTION
Issue 2.4 - November 8, 2001
13/71
2.2 SIGNAL DESCRIPTIONS
2.2.1 BASIC CLOCKS AND RESETS
SYSRSTI System Reset/Power good. This input is
low when the reset switch is depressed. Other-
wise, it reflects the power supply’s power good
signal. SYSRSTI is asynchronous to all clocks,
and acts as a negative active reset. The reset cir-
cuit initiates a hard reset on the rising edge of
SYSRSTI.
SYSRSTO# Reset Output to System. This is the
system reset signal and is used to reset the rest of
the components (not on Host bus) in the system.
The ISA bus reset is an externally inverted buff-
ered version of this output and the PCI bus reset is
an externally buffered version of this output.
XTALI 14.3MHz Crystal Input
XTALO 14.3MHz Crystal Output. These pins are
the 14.318 MHz crystal input; This clock is used as
the reference clock for the internal frequency syn-
thesizer
to
generate
the
HCLK,
CLK24M,
GCLK2X and DCLK clocks.
A 14.318 MHz Series Cut Quartz Crystal should
be connected between these two pins. Balance
capacitors of 15 pF should also be added. In the
event of an external oscillator providing the master
clock signal to the STPC Consumer device, the
TTL signal should be provided on XTALO.
HCLK Host Clock. This is the host 1X clock. Its
frequency can vary from 25 to 75 MHz. All host
transactions and PCI transactions are synchro-
nized to this clock. The DRAM controller to exe-
cute the host transactions is also driven by this
clock. In normal mode, this output clock is gener-
ated by the internal pll.
GCLK2X 80MHz Graphics Clock. This is the
Graphics 2X clock, which drives the graphics en-
gine and the DRAM controller to execute the
graphics and display cycles.
Normally GCLK2X is generated by the internal fre-
quency synthesizer, and this pin is an output. By
setting a bit in Strap Register 2, this pin can be
made an input so that an external clock can re-
place the internal frequency synthesizer.
PCI_CLKI 33MHz PCI Input Clock
This signal is the PCI bus clock input and should
be driven from the PCI_CLKO pin.
PCI_CLKO 33MHz PCI Output Clock. This is the
master PCI bus clock output.
DCLK 135MHz Dot Clock. This is the dot clock,
which drives graphics display cycles. Its frequency
can go from 8MHz (using internal PLL) up to 135
MHz, and it is required to have a worst case duty
cycle of 60-40.
This signal is either driven by the internal pll (VGA)
or an external 27MHz oscillator (when the com-
posite video output is enabled). The direction can
be controlled by a strap option or an internal regis-
ter bit.
ISA_CLK ISA Clock Output (also Multiplexer Se-
lect Line For IPC). This pin produces the Clock
signal for the ISA bus. It is also used with
ISA_CLK2X as the multiplexor control lines for the
Interrupt Controller Interrupt input lines. This is a
divided down version of either the PCICLK or
OSC14M.
ISA_CLKX2 ISA Clock Output (also Multiplexer
Select Line For IPC). This pin produces a signal
that is twice the frequency of the ISA bus Clock
signal. It is also used with ISA_CLK as the multi-
plexor control lines for the Interrupt Controller in-
put lines.
DEV_CLK 24MHz Peripheral Clock Output. This
24MHZ signal is provided as a convenience for
the system integration of a Floppy Disk driver
function in an external chip.
OSC14M ISA bus synchronisation clock Output.
This is the buffered 14.318 Mhz clock to the ISA
bus.
2.2.2 MEMORY INTERFACE
MA[11:0] Memory Address Output. These 12 mul-
tiplexed memory address pins support external
DRAM with up to 4K refresh. These include all
16M x N and some 4M x N DRAM modules. The
address signals must be externally buffered to
support more than 16 DRAM chips. The timing of
these signals can be adjusted by software to
match the timings of most DRAM modules.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STPCC0310BTC3 | MULTIFUNCTION PERIPHERAL, PBGA388 |
| STPCC0390BTC3 | MULTIFUNCTION PERIPHERAL, PBGA388 |
| STPCD0110BTC3 | 32-BIT, 100 MHz, MICROPROCESSOR, PBGA388 |
| STPCD0112BTC3 | 32-BIT, 120 MHz, MICROPROCESSOR, PBGA388 |
| STPCI2EEYC | MULTIFUNCTION PERIPHERAL, PBGA516 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STPCC0175BTC3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| STPCC0180BTC3 | 功能描述:微處理器 - MPU 80MHz x86 Embedded RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| STPCC0180BTI3 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:PC Compatible Embeded Microprocessor |
| STPCC03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:STPC CONSUMER-S DATASHEET/ PC COMPATIBLE EMBEDDED MICROPROCESSOR |
| STPCC0310BTC3 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:PC Compatible Embeded Microprocessor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。