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參數(shù)資料
| 型號： | STPCCONSUMER |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁數(shù)： | 28/51頁 |
| 文件大?。?/td> | 726K |
| 代理商： | STPCCONSUMER |
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STRAP OPTION
28/51
Issue 1.2
Note;
1) This Strap Option selects between two different
functional blocks, the first is the ISA (SMEMW#)
and the other is the VGA block (Color_Key).
2) Setting of Strap Options MD [2:15] have no ef-
fect on the DRAM Controller but are purely meant
for software issues. i.e. Readable in a register.
3.1 STRAP REGISTER DESCRIPTION
3.1.1
(STRAP0)
STRAP
REGISTER
0
INDEX
4AH
Bits 7-0 of this register reflect the status of pins
MD[7:0] respectively. They are expected to be
connected on the system board to the SIMM con-
figuration pins as follows:
Note that the SIMM speed and type information
read here is meant only for thesoftware and is not
used by the hardware. The software must pro-
gram the Host and graphics dram controller con-
figuration registers appropriately based on these
bits.
This register defaults to the values sampled on
MD[7:0] pins after reset.
3.1.2
(STRAP1)
STRAP
REGISTER
1
INDEX
4BH
Bits 7-0 of this register reflect the status of pins
MD[15:8] respectively. They are expected to be
connected on the system board to the SIMM con-
figuration pins as follows:
Note that the SIMM speed and type information
read here is meant only for thesoftware and is not
used by the hardware. The software must pro-
gram the Host and graphics dram controller con-
figuration registers appropriately based on these
bits.
This register defaults to the values sampled on
MD[15:8] pins after reset.
3.1.3
(STRAP2)
STRAP
REGISTER
2
INDEX
4CH
Bits 4-0 of this register reflect the status of pins
MD[20:16] respectively. Bit 5 of this register reflect
the status of pin MD[23]. Bit 4 is writeable, writes
to other bits in this register have no effect.
They are use by the chip as follows:
Bit 4-2; Reserved
MD38
MD39
MD40
MD41
MD42
MD43
-
-
Reserved
Reserved
CPU Mode
Reserved
Reserved
Reserved
-
-
Pull up
Pull up
User defined
Pull down
Pull up
Pull down
-
-
-
-
CPU
-
-
-
DX1
-
-
-
DX2
-
-
-
-
-
-
Memory
Data
Lines
Note
Refer to
Designation
Location
Actual
Settings
Set to ’0’
Set to ’1’
Bit Sampled
Bit 7
Bits 6-5
Bit 4
Bits 3-2
Bits 1-0
Description
SIMM 0 dram type
SIMM 0 speed
SIMM 1 dram type
SIMM 1 speed
Reserved
Bit Sampled
Bit 7
Bits 6-5
Bit 4
Bits 3-2
Description
SIMM 2 dram type
SIMM 2 speed
SIMM 3 dram type
SIMM 3 speed
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