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參數(shù)資料
| 型號： | STPCI0180BTC3 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 微處理器 |
| 英文描述： | PC Compatible Embedded Microprocessor |
| 中文描述： | PC兼容嵌入式微處理器 |
| 文件頁數(shù)： | 22/55頁 |
| 文件大?。?/td> | 787K |
| 代理商： | STPCI0180BTC3 |
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PIN DESCRIPTION
22/55
Issue 1.1
3.2. SIGNAL DESCRIPTIONS
3.2.2 BASIC CLOCKS AND RESETS
SYSRSTI#
System Reset/Power good. This input
is low when the reset switch is depressed. Other-
wise, it reflects the power supply’s power good
signal. PWGD is asynchronous to all clocks, and
acts as a negative active reset. The reset circuit
initiates a hard reset on the rising edge of PWGD.
SYSRSTO#
Reset Output to System. This is the
system resetsignal and is used to reset the rest of
the components (not on Host bus) in the system.
The ISA bus reset is an externally inverted buff-
ered version of this output and the PCI bus resetis
an externally buffered version of this output.
XTALI
14.3MHz Crystal Input
XTALO
14.3MHz Crystal Output. These pins are
the 14.318MHz crystal input; This clock isused as
the reference clock for the internal frequency syn-
thesizer to generate the HCLK and CLK24M.
A 14.318 MHz Series Cut Quartz Crystal should
be connected between these two pins. Balance
capacitors of 15 pF should also be added. In the
event ofan external oscillatorproviding the master
clock signal to theSTPC Industrialdevice, the TTL
signal should be providedon XTALO.
PCI_CLKI
33MHz PCI Input Clock
This signal must be connected to a clock genera-
tor and is usually connected to PCI_CLKO.
PCI_CLKO
33MHz PCI Output Clock. This is the
master PCI bus clock output
ISA_CLK
ISA Clock Output (also Multiplexer Se-
lect Line For IPC). This pin produces the Clock
signal for the ISA bus. It is also used with
ISA_CLK2X as the multiplexor control lines for the
Interrupt Controller Interrupt input lines. This is a
divided down version of the PCICLK or OSC14M.
ISA_CLKX2
ISA Clock Output (also Multiplexer
Select Line For IPC).This pin produces a signal at
twice the frequency of the ISA bus Clock signal. It
is also used with ISA_CLK as the multiplexor con-
trol lines for the Interrupt Controller Interrupt input
lines.
CLK14M
ISA bus synchronisation clock. This is
the buffered 14.318 Mhzclock to the ISA bus. This
clock also provides the reference clock to the fre-
quency synthesizer that generates GCLK2X and
DCLK.
HCLK
Host Clock. This is the host 1X clock. Its
frequency can vary from 50 to 75 MHz. All host
transactions and PCI transactions are synchro-
nized to this clock. Host transactions executed by
the DRAM controller are also driven by this clock.
DEV_CLK
24MHz Peripheral Clock (floppydrive).
This 24MHZ signal is provided as a convenience
for the system integration of a Floppy Disk driver
function in an external chip.
GCLK2X
80MHz Graphics Clock. This is the
Graphics 2X clock, which drives the graphics en-
gine and the DRAM controller to execute the
graphics and display cycles.
Normally GCLK2X isgenerated by the internal fre-
quency synthesizer, and this pin is an output. By
setting a bit in Strap Register 2, this pin can be
made an input so that an external clock can re-
place the internal frequency synthesizer.
DCLK
135MHz Dot Clock. This is the dot clock,
which drivesgraphics display cycles. Its frequency
can be as high as 135 MHz, and it is required to
have a worst case duty cycle of 60-40. For further
details, refer to Section 2.1.3 bit 4.
3.2.3 MEMORY INTERFACE
MA[11:0]
Memory Address.These 12 multiplexed
memory addresspins supportexternal DRAM with
up to 4K refresh. These include all 16M x N and
some 4M x N DRAM modules. The address sig-
nals must be externally buffered to support more
than 16 DRAM chips. The timing of these signals
can be adjusted by software to match the timings
of most DRAM modules.
MD[63:0]
Memory Data.This is the 64-bit memory
data bus. If only half of a bank is populated,
MD63-32 is pulled high, data is on MD31-0.
MD20-0 are also used as inputs at the rising edge
of PWGD to latch in power-up configuration infor-
mation into the ADPC strap registers.
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