參數(shù)資料
型號: STPCI2HDYI
廠商: STMICROELECTRONICS
元件分類: 外設(shè)及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA516
封裝: PLASTIC, BGA-516
文件頁數(shù): 58/109頁
文件大?。?/td> 2430K
代理商: STPCI2HDYI
STPC ATLAS
52/109
Issue 1.1 - March 23, 2004
4.5.3. SDRAM INTERFACE
characteristics of the SDRAM interface. The
MCLKx clocks are the input clock of the SDRAM
devices.
The PC100 memory is recommended to reach
90MHz operation.
Figure 4-5. SDRAM Timing Diagram
MCLKI
STPC.output
STPC.input
MCLKx
Tdelay
Tsetup
Thold
Toutput (min)
Toutput (max)
Tcycle
Thigh
Tlow
Table 4-10. SDRAM Bus AC Timings - Commercial Temperature Range
Name
Parameter
Min
Typ
Max
Unit
Tcycle
MCLKI Cycle Time
11
ns
Thigh
MCLKI High Time
4
ns
Tlow
MCLKI Low Time
4
ns
MCLKI Rising Time
1
ns
MCLKI Falling Time
1
ns
Tdelay
MCLKx to MCLKI delay
0.5
1
1.5
ns
Toutput
MCLKI to RAS# Valid
1.6
5.2
ns
MCLKI to CAS# Valid
1.6
5.2
ns
MCLKI to CS# Valid
1.6
5.2
ns
MCLKI to DQM[ ] Outputs Valid
1.35
5.2
ns
MCLKI to MD[ ] Outputs Valid
1.35
5.2
ns
MCLKI to MA[ ] Outputs Valid
1.6
5.2
ns
MCLKI to MWE# Valid
1.6
5.2
ns
Tsetup
MD[63:0] setup to MCKLI
4.7
ns
Thold
MD[63:0] hold from MCKLI
-0.36
2.3
ns
Note: These timings are for a load of 50pF, part running at 100MHz and ReadCLK activated and set to 0
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